forked from M-Labs/artiq
rtio/sed: add lane distributor (untested)
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from migen import *
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from artiq.gateware.rtio import cri
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def layout_lane_io(seqn_width, layout_payload):
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return [
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("we", 1, DIR_M_TO_S),
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("writable", 1, DIR_S_TO_M),
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("seqn", seqn_width, DIR_M_TO_S),
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("payload", layout_payload, DIR_M_TO_S)
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]
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# CRI write happens in 3 cycles:
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# 1. set timestamp
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# 2. set other payload elements and issue write command
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# 3. check status
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class LaneDistributor(Module):
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def __init__(self, lane_count, fifo_size, layout_payload, fine_ts_width):
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if lane_count & (lane_count - 1):
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raise NotImplementedError("lane count must be a power of 2")
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seqn_width = 4*bits_for(fifo_size-1)*lane_count
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self.cri = cri.Interface()
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self.minimum_coarse_timestamp = Signal(64-fine_ts_width)
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self.lane_io = [Record(layout_lane_io(seqn_width, layout_payload))
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for _ in range(lane_count)]
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# # #
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o_status_wait = Signal()
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o_status_underflow = Signal()
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o_status_sequence_error = Signal()
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self.comb += self.cri.o_status.eq(Cat(o_status_wait, o_status_underflow,
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o_status_sequence_error))
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# internal state
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current_lane = Signal(max=lane_count)
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last_coarse_timestamp = Signal(64-fine_ts_width)
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last_lane_coarse_timestamps = Array(Signal(64-fine_ts_width)
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for _ in range(lane_count))
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seqn = Signal(seqn_width)
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# distribute data to lanes
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for lio in lane_io:
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self.comb += [
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lio.seqn.eq(seqn),
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lio.payload.channel.eq(self.cri.chan_sel[:16]),
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lio.payload.timestamp.eq(self.cri.timestamp),
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]
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if hasattr(lio.payload, "address"):
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self.comb += lio.payload.address.eq(self.cri.address)
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if hasattr(lio.payload, "data"):
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self.comb += lio.payload.data.eq(self.cri.data)
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# when timestamp arrives in cycle #1, prepare computations
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coarse_timestamp = self.cri.timestamp[fine_ts_width:]
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timestamp_above_min = Signal()
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timestamp_above_laneA_min = Signal()
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timestamp_above_laneB_min = Signal()
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use_laneB = Signal()
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use_lanen = Signal(max=lane_count)
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self.sync += [
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timestamp_above_min.eq(coarse_timestamp > self.minimum_coarse_timestamp),
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timestamp_above_laneA_min.eq(coarse_timestamp > last_lane_coarse_timestamps[current_lane]),
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timestamp_above_laneB_min.eq(coarse_timestamp > last_lane_coarse_timestamps[current_lane + 1]),
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If(coarse_timestamp <= last_coarse_timestamp,
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use_lanen.eq(current_lane + 1),
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use_laneB.eq(1)
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).Else(
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use_lanen.eq(current_lane),
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use_laneB.eq(0)
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)
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]
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# cycle #2, write
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timestamp_above_lane_min = Signal()
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do_write = Signal()
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do_underflow = Signal()
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do_sequence_error = Signal()
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self.comb += [
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timestamp_above_lane_min.eq(Mux(use_laneB, timestamp_above_laneB_min, timestamp_above_laneA_min)),
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do_write.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & timestamp_above_lane_min),
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do_underflow.eq((self.cri.cmd == cri.commands["write"]) & ~timestamp_above_min),
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do_sequence_error((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & ~timestamp_above_lane_min),
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Array(lio.we for lio in lane_io)[use_lanen].eq(do_write)
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]
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self.sync += [
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If(do_write,
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current_lane.eq(current_lane + 1),
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last_coarse_timestamp.eq(coarse_timestamp),
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last_lane_coarse_timestamps[use_lanen].eq(coarse_timestamp),
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seqn.eq(seqn + 1),
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)
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]
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# cycle #3, read status
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current_lane_writable = Signal()
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self.comb += [
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current_lane_writable.eq((lio.writable for lio in lane_io)[current_lane]),
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o_status_wait.eq(~current_lane_writable)
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]
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self.sync += [
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o_status_underflow.eq(do_underflow),
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o_status_sequence_error(do_sequence_error)
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]
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# current lane has been full, spread events by switching to the next.
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current_lane_writable_r = Signal()
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self.sync += [
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current_lane_writable_r.eq(current_lane_writable),
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If(~current_lane_writable_r & current_lane_writable,
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current_lane.eq(current_lane + 1)
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)
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]
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