From bdd4e52a53b5cad406d38b3d20ad8e3b93a2b2f5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 28 Jan 2019 13:43:52 +0800 Subject: [PATCH] ad9154: support 125MHz RTIO --- artiq/firmware/libboard_artiq/ad9154.rs | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index ff5f08311..a671c32a1 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -70,9 +70,9 @@ fn jesd_jsync(dacno: u8) -> bool { } // ad9154 mode 1 -// linerate 6Gbps -// deviceclock_fpga=150MHz -// deviceclock_dac=600MHz +// linerate 5Gbps or 6Gbps +// deviceclock_fpga 125MHz or 150MHz +// deviceclock_dac 500MHz or 600MHz struct JESDSettings { did: u8, @@ -615,13 +615,18 @@ fn dac_stpl(dacno: u8, m: u8, s: u8) -> Result<(), &'static str> { } fn dac_cfg(dacno: u8) -> Result<(), &'static str> { + #[cfg(rtio_frequency = "125.0")] + const LINERATE: u64 = 5_000_000_000; + #[cfg(rtio_frequency = "150.0")] + const LINERATE: u64 = 5_000_000_000; + spi_setup(dacno); jesd_enable(dacno, false); jesd_prbs(dacno, false); jesd_stpl(dacno, false); clock::spin_us(10000); jesd_enable(dacno, true); - dac_setup(dacno, 6_000_000_000)?; + dac_setup(dacno, LINERATE)?; jesd_enable(dacno, false); clock::spin_us(10000); jesd_enable(dacno, true);