forked from M-Labs/artiq
suservo experimentals: fix rtio ch name changes
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8dc6902c23
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bdae594c79
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@ -104,15 +104,15 @@ index 1d0a72dad1..f7b516a4e7 100644
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:param core_device: Core device name
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"""
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kernel_invariants = {"channel", "core", "pgia", "cplds", "ddses",
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- "ref_period_mu"}
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- "ref_period_mu", "corrected_fs"}
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+ "ref_period_mu", "num_channels", "coeff_sel",
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+ "state_sel", "io_dly_addr", "config_addr",
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+ "write_enable"}
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+ "corrected_fs", "write_enable"}
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def __init__(self, dmgr, channel, pgia_device,
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cpld_devices, dds_devices,
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@@ -83,9 +85,20 @@ def __init__(self, dmgr, channel, pgia_device,
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self.core.coarse_ref_period)
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@@ -83,13 +85,24 @@ def __init__(self, dmgr, channel, pgia_device,
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self.corrected_fs = sampler.Sampler.use_corrected_fs(sampler_hw_rev)
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assert self.ref_period_mu == self.core.ref_multiplier
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+ # The width of parts of the servo memory address depends on the number
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@ -126,6 +126,10 @@ index 1d0a72dad1..f7b516a4e7 100644
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+ self.coeff_sel = 1 << coeff_depth
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+ self.write_enable = 1 << (coeff_depth + 1)
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+
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@staticmethod
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def get_rtio_channels(channel, **kwargs):
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return [(channel, None)]
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@kernel
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def init(self):
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- """Initialize the servo, Sampler and both Urukuls.
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@ -191,9 +195,9 @@ index 1d0a72dad1..f7b516a4e7 100644
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@kernel
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def set_pgia_mu(self, channel, gain):
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@@ -236,6 +262,18 @@ def get_adc(self, channel):
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@@ -242,6 +268,18 @@ def get_adc(self, channel):
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gain = (self.gains >> (channel*2)) & 0b11
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return adc_mu_to_volts(val, gain)
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return adc_mu_to_volts(val, gain, self.corrected_fs)
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+ @kernel
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+ def set_io_update_delays(self, dlys):
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@ -211,7 +215,7 @@ index 1d0a72dad1..f7b516a4e7 100644
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class Channel:
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"""Sampler-Urukul Servo channel
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@@ -256,7 +294,7 @@ def __init__(self, dmgr, channel, servo_device):
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self.dds = self.servo.ddses[self.servo_channel // 4]
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return [(channel, None)]
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@kernel
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- def set(self, en_out, en_iir=0, profile=0):
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@ -80,9 +80,9 @@ index a89cdcca..f7b516a4 100644
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"""
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kernel_invariants = {"channel", "core", "pgia", "cplds", "ddses",
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"ref_period_mu", "num_channels", "coeff_sel",
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- "state_sel", "config_addr", "write_enable"}
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- "corrected_fs", "state_sel", "config_addr", "write_enable"}
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+ "state_sel", "io_dly_addr", "config_addr",
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+ "write_enable"}
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+ "corrected_fs", "write_enable"}
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def __init__(self, dmgr, channel, pgia_device,
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cpld_devices, dds_devices,
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@ -117,7 +117,7 @@ index a89cdcca..f7b516a4 100644
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"""Write to servo memory.
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@@ -245,6 +262,18 @@ class SUServo:
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gain = (self.gains >> (channel*2)) & 0b11
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return adc_mu_to_volts(val, gain)
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return adc_mu_to_volts(val, gain, self.corrected_fs)
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+ @kernel
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+ def set_io_update_delays(self, dlys):
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@ -135,7 +135,7 @@ index a89cdcca..f7b516a4 100644
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class Channel:
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"""Sampler-Urukul Servo channel
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@@ -265,7 +294,7 @@ class Channel:
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self.dds = self.servo.ddses[self.servo_channel // 4]
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return [(channel, None)]
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@kernel
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- def set(self, en_out, en_iir=0, profile=0):
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@ -48,14 +48,14 @@ index 1d0a72dad..a89cdcca4 100644
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:param core_device: Core device name
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"""
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kernel_invariants = {"channel", "core", "pgia", "cplds", "ddses",
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- "ref_period_mu"}
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- "ref_period_mu", "corrected_fs"}
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+ "ref_period_mu", "num_channels", "coeff_sel",
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+ "state_sel", "config_addr", "write_enable"}
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+ "corrected_fs", "state_sel", "config_addr", "write_enable"}
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def __init__(self, dmgr, channel, pgia_device,
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cpld_devices, dds_devices,
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@@ -83,9 +81,19 @@ def __init__(self, dmgr, channel, pgia_device,
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self.core.coarse_ref_period)
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@@ -83,13 +81,23 @@ def __init__(self, dmgr, channel, pgia_device,
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self.corrected_fs = sampler.Sampler.use_corrected_fs(sampler_hw_rev)
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assert self.ref_period_mu == self.core.ref_multiplier
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+ # The width of parts of the servo memory address depends on the number
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@ -68,6 +68,10 @@ index 1d0a72dad..a89cdcca4 100644
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+ self.coeff_sel = 1 << coeff_depth
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+ self.write_enable = 1 << (coeff_depth + 1)
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+
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@staticmethod
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def get_rtio_channels(channel, **kwargs):
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return [(channel, None)]
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@kernel
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def init(self):
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- """Initialize the servo, Sampler and both Urukuls.
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