fastino: monitor probe dacs

2024-07-16 13:12:29 +08:00 · 2024-07-16 13:12:29 +08:00 · bd3bcbce64
commit bd3bcbce64
parent 0952c47934
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/rtio/phy/fastino.py
+++ b/artiq/gateware/rtio/phy/fastino.py
@ -27,6 +27,7 @@ class Fastino(Module):

        # dac data words
        dacs = [Signal(16) for i in range(32)]
+        self.probes = dacs

        header = Record([
            ("cfg", 4),