forked from M-Labs/artiq
urukul: (proto 7) drop att_le
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@ -22,7 +22,6 @@ _SPIT_DDS_RD = 16
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CFG_RF_SW = 0
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CFG_LED = 4
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CFG_PROFILE = 8
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CFG_ATT_LE = 11
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CFG_IO_UPDATE = 12
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CFG_MASK_NU = 16
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CFG_CLK_SEL = 17
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@ -32,10 +31,10 @@ CFG_IO_RST = 20
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@kernel
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def urukul_cfg(rf_sw, led, profile, att_le, io_update, mask_nu,
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def urukul_cfg(rf_sw, led, profile, io_update, mask_nu,
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clk_sel, sync_sel, rst, io_rst):
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return ((rf_sw << CFG_RF_SW) | (led << CFG_LED) |
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(profile << CFG_PROFILE) | (att_le << CFG_ATT_LE) |
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(profile << CFG_PROFILE) |
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(io_update << CFG_IO_UPDATE) | (mask_nu << CFG_MASK_NU) |
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(clk_sel << CFG_CLK_SEL) | (sync_sel << CFG_SYNC_SEL) |
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(rst << CFG_RST) | (io_rst << CFG_IO_RST))
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@ -75,7 +74,7 @@ def urukul_sta_proto_rev(sta):
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# supported hardware and CPLD code version
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STA_PROTO_REV_MATCH = 0x06
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STA_PROTO_REV_MATCH = 0x07
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# chip select (decoded)
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CS_CFG = 1
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@ -122,7 +121,7 @@ class CPLD:
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@kernel
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def init(self, clk_sel=0, sync_sel=0):
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cfg = urukul_cfg(rf_sw=0, led=0, profile=0, att_le=0,
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cfg = urukul_cfg(rf_sw=0, led=0, profile=0,
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io_update=0, mask_nu=0, clk_sel=clk_sel,
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sync_sel=sync_sel, rst=0, io_rst=0)
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self.cfg_write(cfg | (1 << CFG_RST) | (1 << CFG_IO_RST))
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@ -164,8 +163,6 @@ class CPLD:
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self.bus.set_config_mu(_SPI_CONFIG, _SPIT_ATT_WR, _SPIT_ATT_RD)
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self.bus.set_xfer(CS_ATT, 32, 0)
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self.bus.write(a)
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self.cfg_write(self.cfg_reg | (1 << CFG_ATT_LE))
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self.cfg_write(self.cfg_reg & ~(1 << CFG_ATT_LE))
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@kernel
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def set_att(self, channel, att):
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