diff --git a/artiq/gateware/eem.py b/artiq/gateware/eem.py
index 1bcb71c12..5b5180239 100644
--- a/artiq/gateware/eem.py
+++ b/artiq/gateware/eem.py
@@ -443,15 +443,16 @@ class SUServo(_EEM):
 
     @classmethod
     def add_std(cls, target, eems_sampler, eems_urukul0, eems_urukul1,
-                t_rtt=8, clk=1, shift=11, profile=5):
-        """ Adds an 8-channel Sampler-Urukul servo to target.
+                t_rtt=4, clk=1, shift=11, profile=5):
+        """Add a 8-channel Sampler-Urukul Servo
 
         :param t_rtt: upper estimate for clock round-trip propagation time from
-            sck at the FPGA to clkout at the FPGA, measured in RTIO coarse
-            cycles (default: 8). This is the sum of the round-trip cabling
-            delay and the 8ns max propagation delay on Sampler. With all
-            other parameters at their default values, increasing t_rtt beyond 8
-            increases the servo latency
+            ``sck`` at the FPGA to ``clkout`` at the FPGA, measured in RTIO
+            coarse cycles (default: 4). This is the sum of the round-trip
+            cabling delay and the 8 ns max propagation delay on Sampler (ADC
+            and LVDS drivers). Increasing ``t_rtt`` increases servo latency.
+            With all other parameters at their default values, ``t_rtt`` values
+            above 4 also increase the servo period (reduce servo bandwidth).
         :param clk: DDS SPI clock cycle half-width in RTIO coarse cycles
             (default: 1)
         :param shift: fixed-point scaling factor for IIR coefficients
@@ -459,7 +460,6 @@ class SUServo(_EEM):
         :param profile: log2 of the number of profiles for each DDS channel
             (default: 5)
         """
-
         cls.add_extension(
             target, *(eems_sampler + eems_urukul0 + eems_urukul1))
         eem_sampler = "sampler{}".format(eems_sampler[0])
@@ -468,11 +468,12 @@ class SUServo(_EEM):
 
         sampler_pads = servo_pads.SamplerPads(target.platform, eem_sampler)
         urukul_pads = servo_pads.UrukulPads(
-                target.platform, eem_urukul0, eem_urukul1)
+            target.platform, eem_urukul0, eem_urukul1)
         # timings in units of RTIO coarse period
         adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4,
-                                # account for SCK pipeline latency
-                                t_conv=57 - 4, t_rtt=t_rtt)
+                                # account for SCK DDR to CONV latency
+                                # difference (4 cycles measured)
+                                t_conv=57 - 4, t_rtt=t_rtt + 4)
         iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
                                 accu=48, shift=shift, channel=3,
                                 profile=profile)