From bb0b8a6c002d00f1d727bdbe02279b2c4152ec92 Mon Sep 17 00:00:00 2001 From: linuswck Date: Fri, 3 Nov 2023 10:24:54 +0800 Subject: [PATCH] kasli: Correct the GTP TX clock path during init - TXOUT must be fed back into TXUSRCLK during initialization - Now, MMCM Clock Input is switched before GTP TX Init is started instead of after GTP TX Init is done - Reset in Sys Clock domain is kept asserted when clock is switched and GTP TX Init is NOT done --- artiq/firmware/runtime/rtio_clocking.rs | 2 +- artiq/firmware/satman/main.rs | 2 +- artiq/gateware/drtio/transceiver/gtp_7series.py | 8 ++++---- artiq/gateware/drtio/transceiver/gtp_7series_init.py | 4 ++-- artiq/gateware/targets/kasli.py | 6 ++++-- 5 files changed, 12 insertions(+), 10 deletions(-) diff --git a/artiq/firmware/runtime/rtio_clocking.rs b/artiq/firmware/runtime/rtio_clocking.rs index edb1b74e8..3f11da950 100644 --- a/artiq/firmware/runtime/rtio_clocking.rs +++ b/artiq/firmware/runtime/rtio_clocking.rs @@ -255,7 +255,7 @@ pub fn init() { }; if switched == 0 { info!("Switching sys clock, rebooting..."); - clock::spin_us(500); // delay for clean UART log + clock::spin_us(3000); // delay for clean UART log unsafe { // clock switch and reboot will begin after TX is initialized // and TX will be initialized after this diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index 4ca8c308c..f844abd1e 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -571,7 +571,7 @@ fn sysclk_setup() { si5324::setup(&SI5324_SETTINGS, si5324::Input::Ckin1).expect("cannot initialize Si5324"); info!("Switching sys clock, rebooting..."); // delay for clean UART log, wait until UART FIFO is empty - clock::spin_us(1300); + clock::spin_us(3000); unsafe { csr::gt_drtio::stable_clkin_write(1); } diff --git a/artiq/gateware/drtio/transceiver/gtp_7series.py b/artiq/gateware/drtio/transceiver/gtp_7series.py index 75c31a486..a5c0d0c00 100644 --- a/artiq/gateware/drtio/transceiver/gtp_7series.py +++ b/artiq/gateware/drtio/transceiver/gtp_7series.py @@ -18,7 +18,7 @@ class GTPSingle(Module): # # # - self.stable_clkin = Signal() + self.clk_path_ready = Signal() self.txenable = Signal() self.submodules.encoder = encoder = Encoder(2, True) self.submodules.decoders = decoders = [ClockDomainsRenamer("rtio_rx")( @@ -40,7 +40,7 @@ class GTPSingle(Module): self.submodules += rx_init self.comb += [ - tx_init.stable_clkin.eq(self.stable_clkin), + tx_init.clk_path_ready.eq(self.clk_path_ready), qpll_channel.reset.eq(tx_init.pllreset), tx_init.plllock.eq(qpll_channel.lock) ] @@ -715,7 +715,7 @@ class GTP(Module, TransceiverInterface): def __init__(self, qpll_channel, data_pads, sys_clk_freq, rtio_clk_freq, master=0): self.nchannels = nchannels = len(data_pads) self.gtps = [] - + self.clk_path_ready = Signal() # # # channel_interfaces = [] @@ -736,7 +736,7 @@ class GTP(Module, TransceiverInterface): TransceiverInterface.__init__(self, channel_interfaces) for n, gtp in enumerate(self.gtps): self.comb += [ - gtp.stable_clkin.eq(self.stable_clkin.storage), + gtp.clk_path_ready.eq(self.clk_path_ready), gtp.txenable.eq(self.txenable.storage[n]) ] diff --git a/artiq/gateware/drtio/transceiver/gtp_7series_init.py b/artiq/gateware/drtio/transceiver/gtp_7series_init.py index 8916c2c36..d7d86c459 100644 --- a/artiq/gateware/drtio/transceiver/gtp_7series_init.py +++ b/artiq/gateware/drtio/transceiver/gtp_7series_init.py @@ -10,7 +10,7 @@ __all__ = ["GTPTXInit", "GTPRXInit"] class GTPTXInit(Module): def __init__(self, sys_clk_freq, mode="single"): - self.stable_clkin = Signal() + self.clk_path_ready = Signal() self.done = Signal() self.restart = Signal() @@ -87,7 +87,7 @@ class GTPTXInit(Module): startup_fsm.act("PLL_RESET", self.pllreset.eq(1), pll_reset_timer.wait.eq(1), - If(pll_reset_timer.done & self.stable_clkin, + If(pll_reset_timer.done & self.clk_path_ready, NextState("GTP_RESET") ) ) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index ca3364398..baf75b6bf 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -326,7 +326,8 @@ class MasterBase(MiniSoC, AMPSoC): txout_buf = Signal() self.specials += Instance("BUFG", i_I=gtp.txoutclk, o_O=txout_buf) - self.crg.configure(txout_buf, clk_sw=gtp.tx_init.done) + self.crg.configure(txout_buf, clk_sw=self.gt_drtio.stable_clkin.storage, ext_async_rst=self.crg.clk_sw_fsm.o_clk_sw & ~gtp.tx_init.done) + self.specials += MultiReg(self.crg.clk_sw_fsm.o_clk_sw & self.crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) @@ -596,7 +597,8 @@ class SatelliteBase(BaseSoC, AMPSoC): gtp = self.gt_drtio.gtps[0] txout_buf = Signal() self.specials += Instance("BUFG", i_I=gtp.txoutclk, o_O=txout_buf) - self.crg.configure(txout_buf, clk_sw=gtp.tx_init.done) + self.crg.configure(txout_buf, clk_sw=self.gt_drtio.stable_clkin.storage, ext_async_rst=self.crg.clk_sw_fsm.o_clk_sw & ~gtp.tx_init.done) + self.specials += MultiReg(self.crg.clk_sw_fsm.o_clk_sw & self.crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)