From bae5b73155159c61e47e5cd8056a9dd35a240e6f Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 11 Oct 2016 19:50:19 +0200 Subject: [PATCH] phaser: comment out stpl test --- artiq/gateware/targets/kc705.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 56d9e97fe..520a0d5f4 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -544,13 +544,14 @@ class Phaser(_NIST_Ions): # while at 5 GBps, take every second sample... FIXME self.comb += conv.eq(Cat(ch.o[::2])) - # short transport layer test pattern - self.comb += [ - self.ad9154.jesd_core.transport.sink.converter0.eq(0x01230123), - self.ad9154.jesd_core.transport.sink.converter1.eq(0x45674567), - self.ad9154.jesd_core.transport.sink.converter2.eq(0x89ab89ab), - self.ad9154.jesd_core.transport.sink.converter3.eq(0xcdefcdef) - ] + if False: + # short transport layer test pattern + self.comb += [ + self.ad9154.jesd_core.transport.sink.converter0.eq(0x01230123), + self.ad9154.jesd_core.transport.sink.converter1.eq(0x45674567), + self.ad9154.jesd_core.transport.sink.converter2.eq(0x89ab89ab), + self.ad9154.jesd_core.transport.sink.converter3.eq(0xcdefcdef) + ] self.comb += jesd_sync.eq(self.ad9154.jesd_sync)