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drtio/gtx_7series: paranoid reset deglitching

This commit is contained in:
Sebastien Bourdeauducq 2016-11-02 18:30:22 +08:00
parent 00100148f1
commit ba58a8affd
1 changed files with 8 additions and 2 deletions
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10
artiq/gateware/drtio/transceiver/gtx_7series.py
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@ -162,15 +162,21 @@ class GTX_1000BASE_BX10(Module):
o_GTXTXN=tx_pads.n, o_GTXTXN=tx_pads.n,
) )
tx_reset_deglitched = Signal()
tx_reset_deglitched.attr.add("no_retiming")
self.sync += tx_reset_deglitched.eq(~tx_init.done)
self.clock_domains.cd_rtio = ClockDomain() self.clock_domains.cd_rtio = ClockDomain()
self.specials += [ self.specials += [
Instance("BUFG", i_I=txoutclk, o_O=self.cd_rtio.clk), Instance("BUFG", i_I=txoutclk, o_O=self.cd_rtio.clk),
AsyncResetSynchronizer(self.cd_rtio, ~tx_init.done) AsyncResetSynchronizer(self.cd_rtio, tx_reset_deglitched)
] ]
rx_reset_deglitched = Signal()
rx_reset_deglitched.attr.add("no_retiming")
self.sync.rtio += rx_reset_deglitched.eq(~rx_init.done)
self.clock_domains.cd_rtio_rx = ClockDomain() self.clock_domains.cd_rtio_rx = ClockDomain()
self.specials += [ self.specials += [
Instance("BUFG", i_I=rxoutclk, o_O=self.cd_rtio_rx.clk), Instance("BUFG", i_I=rxoutclk, o_O=self.cd_rtio_rx.clk),
AsyncResetSynchronizer(self.cd_rtio_rx, ~rx_init.done) AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched)
] ]
self.comb += [ self.comb += [