From ba1d137d199cfc53ce9e4976076a258e6d6c9498 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 14 May 2018 18:47:23 +0800
Subject: [PATCH] ad9914: fix FTW write in regular resolution mode

---
 artiq/coredevice/ad9914.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/coredevice/ad9914.py b/artiq/coredevice/ad9914.py
index af2c2d558..dee917d8c 100644
--- a/artiq/coredevice/ad9914.py
+++ b/artiq/coredevice/ad9914.py
@@ -207,7 +207,7 @@ class AD9914:
         self.write(AD9914_GPIO,      (1 << self.channel) << 1)
 
         self.write(AD9914_REG_DRGFL, ftw & 0xffff)
-        self.write(AD9914_REG_DRGFL, (ftw >> 16) & 0xffff)
+        self.write(AD9914_REG_DRGFH, (ftw >> 16) & 0xffff)
 
         # We need the RTIO fine timestamp clock to be phase-locked
         # to DDS SYSCLK, and divided by an integer self.sysclk_per_mu.