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ad9914: fix FTW write in regular resolution mode

This commit is contained in:
Sebastien Bourdeauducq 2018-05-14 18:47:23 +08:00
parent 56a29b91fc
commit ba1d137d19
1 changed files with 1 additions and 1 deletions
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2
artiq/coredevice/ad9914.py
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@ -207,7 +207,7 @@ class AD9914:
self.write(AD9914_GPIO, (1 << self.channel) << 1)
self.write(AD9914_REG_DRGFL, ftw & 0xffff)
self.write(AD9914_REG_DRGFL, (ftw >> 16) & 0xffff)
self.write(AD9914_REG_DRGFH, (ftw >> 16) & 0xffff)
# We need the RTIO fine timestamp clock to be phase-locked
# to DDS SYSCLK, and divided by an integer self.sysclk_per_mu.