From b8870997d095269fb601a2f97e2e6b104b4a1522 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 24 Jul 2019 10:04:45 +0800 Subject: [PATCH] doc: clarify TTL direction control with buffered cards --- artiq/coredevice/ttl.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py index 78f36ef8b..2bc40ed58 100644 --- a/artiq/coredevice/ttl.py +++ b/artiq/coredevice/ttl.py @@ -138,7 +138,11 @@ class TTLInOut: cursor. There must be a delay of at least one RTIO clock cycle before any - other command can be issued.""" + other command can be issued. + + This method only configures the direction at the FPGA. When using + buffered I/O interfaces, such as the Sinara TTL cards, the buffer + direction must be configured separately in the hardware.""" self.set_oe(True) @kernel @@ -147,7 +151,11 @@ class TTLInOut: cursor. There must be a delay of at least one RTIO clock cycle before any - other command can be issued.""" + other command can be issued. + + This method only configures the direction at the FPGA. When using + buffered I/O interfaces, such as the Sinara TTL cards, the buffer + direction must be configured separately in the hardware.""" self.set_oe(False) @kernel