forked from M-Labs/artiq
RELEASE_NOTES: fix rst formatting further
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@ -41,15 +41,15 @@ Highlights:
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- Synchronization calibration data can be read from EEPROM.
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- Synchronization calibration data can be read from EEPROM.
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* A gateware-level input edge counter has been added, which offers higher
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* A gateware-level input edge counter has been added, which offers higher
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throughput and increased flexibility over the usual TTL input PHYs where
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throughput and increased flexibility over the usual TTL input PHYs where
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edge timestamps are not required. See :mod:`artiq.coredevice.edge_counter` for
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edge timestamps are not required. See `artiq.coredevice.edge_counter` for
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the core device driver and :mod:`artiq.gateware.rtio.phy.edge_counter`/
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the core device driver and `artiq.gateware.rtio.phy.edge_counter`/
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:meth:`artiq.gateware.eem.DIO.add_std` for the gateware components.
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`artiq.gateware.eem.DIO.add_std` for the gateware components.
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* With DRTIO, Siphaser uses a better calibration mechanism.
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* With DRTIO, Siphaser uses a better calibration mechanism.
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See: https://github.com/m-labs/artiq/commit/cc58318500ecfa537abf24127f2c22e8fe66e0f8
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See: https://github.com/m-labs/artiq/commit/cc58318500ecfa537abf24127f2c22e8fe66e0f8
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* Schedule updates can be sent to influxdb (artiq_influxdb_schedule).
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* Schedule updates can be sent to influxdb (artiq_influxdb_schedule).
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* Experiments can now programatically set their default pipeline, priority, and flush flag.
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* Experiments can now programatically set their default pipeline, priority, and flush flag.
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* List datasets can now be efficiently appended to from experiments using
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* List datasets can now be efficiently appended to from experiments using
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:meth:`artiq.language.environment.HasEnvironment.append_to_dataset`.
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`artiq.language.environment.HasEnvironment.append_to_dataset`.
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* The core device now supports IPv6.
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* The core device now supports IPv6.
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* To make development easier, the bootloader can receive firmware and secondary FPGA
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* To make development easier, the bootloader can receive firmware and secondary FPGA
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gateware from the network.
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gateware from the network.
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@ -59,8 +59,8 @@ Highlights:
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Breaking changes:
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Breaking changes:
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* The :class:`~artiq.coredevice.ad9910.AD9910` and
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* The `artiq.coredevice.ad9910.AD9910` and
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:class:`~artiq.coredevice.ad9914.AD9914` phase reference timestamp parameters
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`artiq.coredevice.ad9914.AD9914` phase reference timestamp parameters
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have been renamed to ``ref_time_mu`` for consistency, as they are in machine
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have been renamed to ``ref_time_mu`` for consistency, as they are in machine
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units.
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units.
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* The controller manager now ignores device database entries without the
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* The controller manager now ignores device database entries without the
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