forked from M-Labs/artiq
phaser: 150 MHz rtio/jesd clock
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@ -12,7 +12,7 @@
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {
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"ref_period": 1e-9,
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"ref_period": 5/6,
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"external_clock": True
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}
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},
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@ -54,24 +54,24 @@
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 4, "parallelism": 4}
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"arguments": {"channel_base": 4, "parallelism": 2}
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},
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"sawg1": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 7, "parallelism": 4}
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"arguments": {"channel_base": 7, "parallelism": 2}
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},
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"sawg2": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 10, "parallelism": 4}
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"arguments": {"channel_base": 10, "parallelism": 2}
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},
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"sawg3": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 13, "parallelism": 4}
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"arguments": {"channel_base": 13, "parallelism": 2}
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}
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}
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@ -397,13 +397,13 @@ class _PhaserCRG(Module, AutoCSR):
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
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p_CLKIN1_PERIOD=4.0, p_CLKIN2_PERIOD=4.0,
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p_CLKIN1_PERIOD=20/3, p_CLKIN2_PERIOD=20/3,
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i_CLKIN1=0, i_CLKIN2=refclk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 250MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=2,
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# VCO @ 1.2GHz when using 150MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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@ -419,7 +419,7 @@ class _PhaserCRG(Module, AutoCSR):
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self._pll_locked.status)
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]
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self.cd_rtio.clk.attr.add("keep")
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platform.add_period_constraint(self.cd_rtio.clk, 8.)
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platform.add_period_constraint(self.cd_rtio.clk, 20/3)
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class AD9154JESD(Module, AutoCSR):
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@ -427,9 +427,9 @@ class AD9154JESD(Module, AutoCSR):
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ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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linerate = 10e9
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refclk_freq = 250e6
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fabric_freq = 250*1000*1000
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linerate = 6e9
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refclk_freq = 150e6
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fabric_freq = 150*1000*1000
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sync_pads = platform.request("ad9154_sync")
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self.jsync = Signal()
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@ -494,16 +494,11 @@ class AD9154(Module, AutoCSR):
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self.submodules.jesd = AD9154JESD(platform)
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self.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
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self.sawgs = [sawg.Channel(width=16, parallelism=2) for i in range(4)]
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self.submodules += self.sawgs
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x = Signal()
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y = Signal()
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z = Signal()
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self.sync.jesd += x.eq(~x), z.eq(x == y)
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self.sync.rio_phy += y.eq(x)
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for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
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self.sync.jesd += conv.eq(Mux(z, Cat(ch.o[:2]), Cat(ch.o[2:])))
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self.sync.jesd += conv.eq(Cat(ch.o))
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class Phaser(MiniSoC, AMPSoC):
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