From b6f7698a69ee642d12072d1e290f596c251a05b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Kulik?= Date: Fri, 6 Dec 2019 15:41:19 +0100 Subject: [PATCH] Enabled internal pullup for CML SYSREF outputs, otherwise there is no signal on them. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Paweł Kulik --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index a3e2cf337..2c34f9f0d 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -150,9 +150,9 @@ pub mod hmc7043 { // enabled, divider, output config, is sysref const OUTPUT_CONFIG: [(bool, u16, u8, bool); 14] = [ (true, DAC_CLK_DIV, 0x08, false), // 0: DAC1_CLK - (true, SYSREF_DIV, 0x00, true), // 1: DAC1_SYSREF + (true, SYSREF_DIV, 0x01, true), // 1: DAC1_SYSREF (true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK - (true, SYSREF_DIV, 0x00, true), // 3: DAC0_SYSREF + (true, SYSREF_DIV, 0x01, true), // 3: DAC0_SYSREF (true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0 (true, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1 (false, 0, 0x10, false), // 6: unused