From b6ab59fb80f45a230b486208acae0c0d885c3b51 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 12 May 2018 01:32:55 +0200 Subject: [PATCH] serwb/phy: increase timeout --- artiq/gateware/serwb/phy.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/serwb/phy.py b/artiq/gateware/serwb/phy.py index de7c4144e..d683444b1 100644 --- a/artiq/gateware/serwb/phy.py +++ b/artiq/gateware/serwb/phy.py @@ -21,7 +21,7 @@ from artiq.gateware.serwb.s7phy import S7Serdes @ResetInserter() class _SerdesMasterInit(Module): - def __init__(self, serdes, taps, timeout=2**14): + def __init__(self, serdes, taps, timeout=2**15): self.ready = Signal() self.error = Signal() @@ -154,7 +154,7 @@ class _SerdesMasterInit(Module): @ResetInserter() class _SerdesSlaveInit(Module, AutoCSR): - def __init__(self, serdes, taps, timeout=2**14): + def __init__(self, serdes, taps, timeout=2**15): self.ready = Signal() self.error = Signal() @@ -351,7 +351,7 @@ class _SerdesControl(Module, AutoCSR): class SERWBPHY(Module, AutoCSR): - def __init__(self, device, pads, mode="master", init_timeout=2**14): + def __init__(self, device, pads, mode="master", init_timeout=2**15): self.sink = sink = stream.Endpoint([("data", 32)]) self.source = source = stream.Endpoint([("data", 32)]) assert mode in ["master", "slave"]