From b692981c8e3bbeb48b70846fa8f2a0fb97285bd7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Tue, 22 Jan 2019 11:49:09 +0000
Subject: [PATCH] ad9910: add note about red front panel led
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Signed-off-by: Robert Jördens <rj@quartiq.de>
---
 artiq/coredevice/ad9910.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py
index 5ef117c38..17c3c7a33 100644
--- a/artiq/coredevice/ad9910.py
+++ b/artiq/coredevice/ad9910.py
@@ -79,6 +79,7 @@ class AD9910:
         clk_div is the reference clock divider (both set in the parent
         Urukul CPLD instance).
     :param pll_en: PLL enable bit, set to 0 to bypass PLL (default: 1).
+        Note that when bypassing the PLL the red front panel LED may remain on.
     :param pll_cp: DDS PLL charge pump setting.
     :param pll_vco: DDS PLL VCO range selection.
     :param sync_delay_seed: SYNC_IN delay tuning starting value.