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rename to coeff base and shorter write16

This commit is contained in:
SingularitySurfer 2022-06-21 09:59:40 +00:00
parent 57176fedb2
commit b67a70392d
1 changed files with 3 additions and 5 deletions
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8
artiq/coredevice/phaser.py
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@ -45,7 +45,7 @@ PHASER_ADDR_SERVO_CFG0 = 0x30
PHASER_ADDR_SERVO_CFG1 = 0x31 PHASER_ADDR_SERVO_CFG1 = 0x31
# 0x32 - 0x61 ab regs # 0x32 - 0x61 ab regs
PHASER_ADDR_SERVO_AB_BASE = 0x32 PHASER_ADDR_SERVO_COEFFICIENTS_BASE = 0x32
# 0x62 - 0x71 offset regs # 0x62 - 0x71 offset regs
PHASER_ADDR_SERVO_OFFSET_BASE = 0x62 PHASER_ADDR_SERVO_OFFSET_BASE = 0x62
@ -418,10 +418,8 @@ class Phaser:
@kernel @kernel
def write16(self, addr, data: TInt32): def write16(self, addr, data: TInt32):
"""Write 16 bit to a sequence of FPGA registers.""" """Write 16 bit to a sequence of FPGA registers."""
byte = data >> 8 self.write8(addr, data >> 8)
self.write8(addr, byte) self.write8(addr + 1, data)
byte = data & 0xFF
self.write8(addr + 1, byte)
@kernel @kernel
def write32(self, addr, data: TInt32): def write32(self, addr, data: TInt32):