srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma: style

This commit is contained in:
Sebastien Bourdeauducq 2017-12-15 19:45:51 +08:00
parent 649b60ea29
commit b6199bb35b
2 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -190,9 +190,9 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs +
self.ad9154_1.sawgs
for phy in sawg.phys)
for sawg in self.ad9154_0.sawgs +
self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

1
artiq/gateware/targets/sayma_rtm.py
View File

@ -120,6 +120,7 @@ class SaymaRTM(Module):
self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio))
csr_devices.append("allaki_atts")
# HMC clock chip and DAC control
self.comb += [
platform.request("ad9154_rst_n").eq(1),
platform.request("ad9154_txen", 0).eq(0b11),