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ad9910: make ram read work for short segments 

also cleanup and style

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2019-02-21 14:47:31 +00:00
parent 2a60914cb9
commit b57cad77ad
1 changed files with 17 additions and 13 deletions
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18
artiq/coredevice/ad9910.py
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@ -280,10 +280,12 @@ class AD9910:
self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR, self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
self.chip_select) self.chip_select)
self.bus.write((_AD9910_REG_RAM | 0x80) << 24) self.bus.write((_AD9910_REG_RAM | 0x80) << 24)
n = len(data) - 1
if n > 0:
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_INPUT, 32, self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_INPUT, 32,
urukul.SPIT_DDS_RD, self.chip_select) urukul.SPIT_DDS_RD, self.chip_select)
preload = 8 preload = min(n, 8)
for i in range(len(data) - 1): for i in range(n):
self.bus.write(0) self.bus.write(0)
if i >= preload: if i >= preload:
data[i - preload] = self.bus.read() data[i - preload] = self.bus.read()
@ -292,7 +294,7 @@ class AD9910:
urukul.SPIT_DDS_RD, self.chip_select) urukul.SPIT_DDS_RD, self.chip_select)
self.bus.write(0) self.bus.write(0)
for i in range(preload + 1): for i in range(preload + 1):
data[(len(data) - preload - 1) + i] = self.bus.read() data[(n - preload) + i] = self.bus.read()
@kernel @kernel
def set_cfr1(self, power_down=0b0000, phase_autoclear=0, def set_cfr1(self, power_down=0b0000, phase_autoclear=0,
@ -382,8 +384,8 @@ class AD9910:
self.set_cfr1(power_down=bits) self.set_cfr1(power_down=bits)
self.cpld.io_update.pulse(1*us) self.cpld.io_update.pulse(1*us)
# KLUDGE: ref_time_mu default argument is explicitly marked int64() to avoid # KLUDGE: ref_time_mu default argument is explicitly marked int64() to
# silent truncation of explicitly passed timestamps. (Compiler bug?) # avoid silent truncation of explicitly passed timestamps. (Compiler bug?)
@kernel @kernel
def set_mu(self, ftw, pow_=0, asf=0x3fff, phase_mode=_PHASE_MODE_DEFAULT, def set_mu(self, ftw, pow_=0, asf=0x3fff, phase_mode=_PHASE_MODE_DEFAULT,
ref_time_mu=int64(-1), profile=0): ref_time_mu=int64(-1), profile=0):
@ -446,7 +448,8 @@ class AD9910:
:param start: Profile start address in RAM. :param start: Profile start address in RAM.
:param end: Profile end address in RAM (last address). :param end: Profile end address in RAM (last address).
:param step: Profile address step size (default: 1). :param step: Profile time step in units of t_DDS, typically 4 ns
(default: 1).
:param profile: Profile index (0 to 7) (default: 0). :param profile: Profile index (0 to 7) (default: 0).
:param nodwell_high: No-dwell high bit (default: 0, :param nodwell_high: No-dwell high bit (default: 0,
see AD9910 documentation). see AD9910 documentation).
@ -542,7 +545,8 @@ class AD9910:
""" """
return self.pow_to_turns(self.set_mu( return self.pow_to_turns(self.set_mu(
self.frequency_to_ftw(frequency), self.turns_to_pow(phase), self.frequency_to_ftw(frequency), self.turns_to_pow(phase),
self.amplitude_to_asf(amplitude), phase_mode, ref_time_mu, profile)) self.amplitude_to_asf(amplitude), phase_mode, ref_time_mu,
profile))
@kernel @kernel
def set_att_mu(self, att): def set_att_mu(self, att):