diff --git a/artiq/firmware/runtime/rtio_clocking.rs b/artiq/firmware/runtime/rtio_clocking.rs index cce5d3b7b..c93f4b044 100644 --- a/artiq/firmware/runtime/rtio_clocking.rs +++ b/artiq/firmware/runtime/rtio_clocking.rs @@ -259,14 +259,14 @@ pub fn init() { unsafe { // clock switch and reboot will begin after TX is initialized // and TX will be initialized after this - csr::drtio_transceiver::stable_clkin_write(1); + csr::gt_drtio::stable_clkin_write(1); } loop {} } else { // enable TX after the reboot, with stable clock unsafe { - csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); + csr::gt_drtio::txenable_write(0xffffffffu32 as _); } } } diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index e4452575f..7ef70f553 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -479,7 +479,7 @@ fn sysclk_setup() { // delay for clean UART log, wait until UART FIFO is empty clock::spin_us(1300); unsafe { - csr::drtio_transceiver::stable_clkin_write(1); + csr::gt_drtio::stable_clkin_write(1); } loop {} } @@ -553,7 +553,7 @@ pub extern fn main() -> i32 { #[cfg(not(has_drtio_eem))] unsafe { - csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); + csr::gt_drtio::txenable_write(0xffffffffu32 as _); } init_rtio_crg(); diff --git a/artiq/gateware/eem.py b/artiq/gateware/eem.py index 112cd880f..e683946c5 100644 --- a/artiq/gateware/eem.py +++ b/artiq/gateware/eem.py @@ -30,7 +30,7 @@ class _EEM: target.platform.add_extension(cls.io(eem, *args, **kwargs)) if is_drtio_over_eem: print("{} (EEM{}) starting at DRTIO channel 0x{:06x}" - .format(name, eem, (len(target.drtio_transceiver.channels) + len(target.eem_drtio_channels) + 1) << 16)) + .format(name, eem, (len(target.gt_drtio.channels) + len(target.eem_drtio_channels) + 1) << 16)) else: print("{} (EEM{}) starting at RTIO channel 0x{:06x}" .format(name, eem, len(target.rtio_channels))) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index a9d5f5d2b..f9b94e26c 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -268,17 +268,17 @@ class MasterBase(MiniSoC, AMPSoC): sfp_ctls = [platform.request("sfp_ctl", i) for i in range(1, 3)] self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls] - self.submodules.drtio_transceiver = gtp_7series.GTP( + self.submodules.gt_drtio = gtp_7series.GTP( qpll_channel=self.drtio_qpll_channel, data_pads=drtio_data_pads, sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) - self.csr_devices.append("drtio_transceiver") + self.csr_devices.append("gt_drtio") if enable_sata: - sfp_channels = self.drtio_transceiver.channels[1:] + sfp_channels = self.gt_drtio.channels[1:] else: - sfp_channels = self.drtio_transceiver.channels + sfp_channels = self.gt_drtio.channels if self.platform.hw_rev in ("v1.0", "v1.1"): self.comb += [sfp_ctl.led.eq(channel.rx_ready) for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)] @@ -292,7 +292,7 @@ class MasterBase(MiniSoC, AMPSoC): self.drtioaux_csr_group = [] self.drtioaux_memory_group = [] self.drtio_cri = [] - for i in range(len(self.drtio_transceiver.channels)): + for i in range(len(self.gt_drtio.channels)): core_name = "drtio" + str(i) coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" @@ -302,7 +302,7 @@ class MasterBase(MiniSoC, AMPSoC): cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) - core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i])) + core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i])) setattr(self.submodules, core_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(core_name) @@ -319,7 +319,7 @@ class MasterBase(MiniSoC, AMPSoC): self.config["HAS_DRTIO_ROUTING"] = None rtio_clk_period = 1e9/rtio_clk_freq - gtp = self.drtio_transceiver.gtps[0] + gtp = self.gt_drtio.gtps[0] txout_buf = Signal() self.specials += Instance("BUFG", i_I=gtp.txoutclk, o_O=txout_buf) @@ -331,7 +331,7 @@ class MasterBase(MiniSoC, AMPSoC): platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk) - for gtp in self.drtio_transceiver.gtps[1:]: + for gtp in self.gt_drtio.gtps[1:]: platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.rxoutclk) @@ -372,7 +372,7 @@ class MasterBase(MiniSoC, AMPSoC): cdr = ClockDomainsRenamer({"rtio_rx": "sys"}) for i in range(len(self.eem_transceiver.channels)): - channel = i + len(self.drtio_transceiver.channels) + channel = i + len(self.gt_drtio.channels) core_name = "drtio" + str(channel) coreaux_name = "drtioaux" + str(channel) memory_name = "drtioaux" + str(channel) + "_mem" @@ -504,17 +504,17 @@ class SatelliteBase(BaseSoC, AMPSoC): if self.platform.hw_rev in ("v1.0", "v1.1"): sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)] self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls] - self.submodules.drtio_transceiver = gtp_7series.GTP( + self.submodules.gt_drtio = gtp_7series.GTP( qpll_channel=qpll.channels[0], data_pads=drtio_data_pads, sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) - self.csr_devices.append("drtio_transceiver") + self.csr_devices.append("gt_drtio") if enable_sata: - sfp_channels = self.drtio_transceiver.channels[1:] + sfp_channels = self.gt_drtio.channels[1:] else: - sfp_channels = self.drtio_transceiver.channels + sfp_channels = self.gt_drtio.channels if self.platform.hw_rev in ("v1.0", "v1.1"): self.comb += [sfp_ctl.led.eq(channel.rx_ready) for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)] @@ -528,7 +528,7 @@ class SatelliteBase(BaseSoC, AMPSoC): drtioaux_memory_group = [] drtiorep_csr_group = [] self.drtio_cri = [] - for i in range(len(self.drtio_transceiver.channels)): + for i in range(len(self.gt_drtio.channels)): coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtioaux_csr_group.append(coreaux_name) @@ -539,7 +539,7 @@ class SatelliteBase(BaseSoC, AMPSoC): if i == 0: self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr(DRTIOSatellite( - self.rtio_tsc, self.drtio_transceiver.channels[i], + self.rtio_tsc, self.gt_drtio.channels[i], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") @@ -548,7 +548,7 @@ class SatelliteBase(BaseSoC, AMPSoC): drtiorep_csr_group.append(corerep_name) core = cdr(DRTIORepeater( - self.rtio_tsc, self.drtio_transceiver.channels[i])) + self.rtio_tsc, self.gt_drtio.channels[i])) setattr(self.submodules, corerep_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) @@ -587,7 +587,7 @@ class SatelliteBase(BaseSoC, AMPSoC): self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None - gtp = self.drtio_transceiver.gtps[0] + gtp = self.gt_drtio.gtps[0] txout_buf = Signal() self.specials += Instance("BUFG", i_I=gtp.txoutclk, o_O=txout_buf) self.crg.configure(txout_buf, clk_sw=gtp.tx_init.done) @@ -597,7 +597,7 @@ class SatelliteBase(BaseSoC, AMPSoC): platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk) - for gtp in self.drtio_transceiver.gtps[1:]: + for gtp in self.gt_drtio.gtps[1:]: platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.rxoutclk) diff --git a/artiq/gateware/targets/kasli_generic.py b/artiq/gateware/targets/kasli_generic.py index 072a22b3e..da92af8ef 100755 --- a/artiq/gateware/targets/kasli_generic.py +++ b/artiq/gateware/targets/kasli_generic.py @@ -108,7 +108,7 @@ class GenericMaster(MasterBase): self.add_csr_group("grabber", self.grabber_csr_group) for grabber in self.grabber_csr_group: self.platform.add_false_path_constraints( - self.drtio_transceiver.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk) + self.gt_drtio.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk) class GenericSatellite(SatelliteBase): @@ -142,7 +142,7 @@ class GenericSatellite(SatelliteBase): self.add_csr_group("grabber", self.grabber_csr_group) for grabber in self.grabber_csr_group: self.platform.add_false_path_constraints( - self.drtio_transceiver.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk) + self.gt_drtio.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk) def main(): diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 884586f07..1c62476e5 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -215,11 +215,11 @@ class _MasterBase(MiniSoC, AMPSoC): ] # 1000BASE_BX10 Ethernet compatible, 100/125MHz RTIO clock - self.submodules.drtio_transceiver = gtx_7series.GTX( + self.submodules.gt_drtio = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, clk_freq=self.clk_freq) - self.csr_devices.append("drtio_transceiver") + self.csr_devices.append("gt_drtio") self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) @@ -227,7 +227,7 @@ class _MasterBase(MiniSoC, AMPSoC): drtioaux_csr_group = [] drtioaux_memory_group = [] self.drtio_cri = [] - for i in range(len(self.drtio_transceiver.channels)): + for i in range(len(self.gt_drtio.channels)): core_name = "drtio" + str(i) coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" @@ -238,7 +238,7 @@ class _MasterBase(MiniSoC, AMPSoC): cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)}) core = cdr(DRTIOMaster( - self.rtio_tsc, self.drtio_transceiver.channels[i])) + self.rtio_tsc, self.gt_drtio.channels[i])) setattr(self.submodules, core_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(core_name) @@ -257,7 +257,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) - self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) + self.config["RTIO_FREQUENCY"] = str(self.gt_drtio.rtio_clk_freq/1e6) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") @@ -266,10 +266,10 @@ class _MasterBase(MiniSoC, AMPSoC): self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None - rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq + rtio_clk_period = 1e9/self.gt_drtio.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) - gtx0 = self.drtio_transceiver.gtxs[0] + gtx0 = self.gt_drtio.gtxs[0] txout_buf = Signal() self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) @@ -286,7 +286,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.crg.cd_sys.clk, gtx0.rxoutclk) # Constrain RX timing for the each transceiver channel # (Each channel performs single-lane phase alignment for RX) - for gtx in self.drtio_transceiver.gtxs[1:]: + for gtx in self.gt_drtio.gtxs[1:]: platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtx.rxoutclk) @@ -363,11 +363,11 @@ class _SatelliteBase(BaseSoC, AMPSoC): rtio_clk_freq = clk_freq # 1000BASE_BX10 Ethernet compatible, 100/125MHz RTIO clock - self.submodules.drtio_transceiver = gtx_7series.GTX( + self.submodules.gt_drtio = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, clk_freq=self.clk_freq) - self.csr_devices.append("drtio_transceiver") + self.csr_devices.append("gt_drtio") self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) @@ -375,7 +375,7 @@ class _SatelliteBase(BaseSoC, AMPSoC): drtioaux_memory_group = [] drtiorep_csr_group = [] self.drtio_cri = [] - for i in range(len(self.drtio_transceiver.channels)): + for i in range(len(self.gt_drtio.channels)): coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem" drtioaux_csr_group.append(coreaux_name) @@ -387,7 +387,7 @@ class _SatelliteBase(BaseSoC, AMPSoC): if i == 0: self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer()) core = cdr(DRTIOSatellite( - self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer)) + self.rtio_tsc, self.gt_drtio.channels[0], self.rx_synchronizer)) self.submodules.drtiosat = core self.csr_devices.append("drtiosat") # Repeaters @@ -395,7 +395,7 @@ class _SatelliteBase(BaseSoC, AMPSoC): corerep_name = "drtiorep" + str(i-1) drtiorep_csr_group.append(corerep_name) core = cdr(DRTIORepeater( - self.rtio_tsc, self.drtio_transceiver.channels[i])) + self.rtio_tsc, self.gt_drtio.channels[i])) setattr(self.submodules, corerep_name, core) self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) @@ -414,14 +414,14 @@ class _SatelliteBase(BaseSoC, AMPSoC): self.add_memory_group("drtioaux_mem", drtioaux_memory_group) self.add_csr_group("drtiorep", drtiorep_csr_group) - self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) + self.config["RTIO_FREQUENCY"] = str(self.gt_drtio.rtio_clk_freq/1e6) # Si5324 Phaser self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin_33"), rx_synchronizer=self.rx_synchronizer, ref_clk=ClockSignal("bootstrap"), ultrascale=False, - rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) + rtio_clk_freq=self.gt_drtio.rtio_clk_freq) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") @@ -433,10 +433,10 @@ class _SatelliteBase(BaseSoC, AMPSoC): self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None - rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq + rtio_clk_period = 1e9/self.gt_drtio.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) - gtx0 = self.drtio_transceiver.gtxs[0] + gtx0 = self.gt_drtio.gtxs[0] txout_buf = Signal() self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) @@ -451,7 +451,7 @@ class _SatelliteBase(BaseSoC, AMPSoC): platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period) # Constrain RX timing for the each transceiver channel # (Each channel performs single-lane phase alignment for RX) - for gtx in self.drtio_transceiver.gtxs[1:]: + for gtx in self.gt_drtio.gtxs[1:]: platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtx.rxoutclk)