From b548d50a2f099bfa56c67bd36e450636290e40fc Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 29 Jul 2015 19:42:43 +0800
Subject: [PATCH] test/coredevice: use ttl_out for PulseRate (loop is less
 available)

---
 artiq/test/coredevice.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/artiq/test/coredevice.py b/artiq/test/coredevice.py
index e4d9375ba..7ae1dc336 100644
--- a/artiq/test/coredevice.py
+++ b/artiq/test/coredevice.py
@@ -76,7 +76,7 @@ class ClockGeneratorLoopback(EnvExperiment):
 class PulseRate(EnvExperiment):
     def build(self):
         self.attr_device("core")
-        self.attr_device("loop_out")
+        self.attr_device("ttl_out")
 
     def set_pulse_rate(self, pulse_rate):
         self.set_result("pulse_rate", pulse_rate)
@@ -87,7 +87,7 @@ class PulseRate(EnvExperiment):
         while True:
             try:
                 for i in range(1000):
-                    self.loop_out.pulse_mu(dt)
+                    self.ttl_out.pulse_mu(dt)
                     delay_mu(dt)
             except RTIOUnderflow:
                 dt += 1