From b492aad1c421e55b50de8c2c81c5fd499bedbf79 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 10 Apr 2015 13:15:32 +0800 Subject: [PATCH] targets/kc705: enable Ethernet core --- soc/targets/artiq_kc705.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index e56f1dc59..e3bb0095b 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -5,7 +5,7 @@ from mibuild.generic_platform import * from misoclib.com import gpio from misoclib.soc import mem_decoder -from targets.kc705 import BaseSoC +from targets.kc705 import MiniSoC from artiq.gateware import amp, rtio, ad9858, nist_qc1 @@ -28,15 +28,15 @@ class _RTIOCRG(Module, AutoCSR): o_O=self.cd_rtio.clk) -class _Peripherals(BaseSoC): +class _Peripherals(MiniSoC): csr_map = { "rtio": None, # mapped on Wishbone instead "rtiocrg": 13 } - csr_map.update(BaseSoC.csr_map) + csr_map.update(MiniSoC.csr_map) def __init__(self, platform, cpu_type="or1k", **kwargs): - BaseSoC.__init__(self, platform, + MiniSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs) platform.add_extension(nist_qc1.fmc_adapter_io)