forked from M-Labs/artiq
metlino: work around vivado bug (#1230)
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@ -65,7 +65,8 @@ class Master(MiniSoC, AMPSoC):
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean", 0),
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data_pads=[platform.request("mch_fabric_d", i) for i in range(12)],
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# use only a few channels to work around Vivado bug
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data_pads=[platform.request("mch_fabric_d", i) for i in range(3)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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