forked from M-Labs/artiq
phaser: rework docs
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@ -57,11 +57,11 @@ class Phaser:
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Phaser contains a 4 channel, 1 GS/s DAC chip with integrated upconversion,
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quadrature modulation compensation and interpolation features.
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The coredevice produces 2 IQ data streams with 25 MS/s and 14 bit per
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quadrature. Each data stream supports 5 independent numerically controlled
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IQ oscillators (NCOs, DDSs with 32 bit frequency, 16 bit phase, 15 bit
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amplitude, and phase accumulator clear functionality) added together.
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See :class:`PhaserChannel` and :class:`PhaserOscillator`.
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The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25
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MS/s and 14 bit per quadrature. Each data stream supports 5 independent
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numerically controlled IQ oscillators (NCOs, DDSs with 32 bit frequency, 16
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bit phase, 15 bit amplitude, and phase accumulator clear functionality)
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added together. See :class:`PhaserChannel` and :class:`PhaserOscillator`.
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Together with a data clock, framing marker, a checksum and metadata for
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register access the streams are sent in groups of 8 samples over 1.5 Gb/s
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@ -91,13 +91,13 @@ class Phaser:
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attenuators and are available on the front panel. The odd outputs are
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available at MMCX connectors on board.
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In the upconverter variant, each of the two IQ (in-phase and quadrature)
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output pairs feeds a one quadrature upconverter with integrated PLL/VCO.
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This analog quadrature upconverter supports offset tuning for carrier and
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sideband suppression. The output from the upconverter passes through the
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31.5 dB range step attenuator and is available at the front panel.
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In the upconverter variant, each IQ output pair feeds a one quadrature
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upconverter with integrated PLL/VCO. This analog quadrature upconverter
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supports offset tuning for carrier and sideband suppression. The output
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from the upconverter passes through the 31.5 dB range step attenuator and
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is available at the front panel.
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The DAC, the analog quadrature upconverters and the two attenuators are
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The DAC, the analog quadrature upconverters and the attenuators are
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configured through a shared SPI bus that is accessed and controlled via
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FPGA registers.
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@ -373,7 +373,8 @@ class PhaserChannel:
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The data is split accross multiple registers and thus the data
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is only valid if constant.
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:return: DAC data as 32 bit IQ. I in the 16 LSB, Q in the 16 MSB
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:return: DAC data as 32 bit IQ. I/DACA/DACC in the 16 LSB,
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Q/DACB/DACD in the 16 MSB
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"""
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return self.phaser.read32(PHASER_ADDR_DAC0_DATA + (self.index << 4))
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@ -381,7 +382,8 @@ class PhaserChannel:
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def set_dac_test(self, data: TInt32):
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"""Set the DAC test data.
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:param data: 32 bit IQ test data, I in the 16 LSB, Q in the 16 MSB
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:param data: 32 bit IQ test data, I/DACA/DACC in the 16 LSB,
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Q/DACB/DACD in the 16 MSB
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"""
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self.phaser.write32(PHASER_ADDR_DAC0_TEST + (self.index << 4), data)
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