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phaser: tag jesd as clock net

This commit is contained in:
Robert Jördens 2016-10-14 10:46:33 +02:00
parent 4ea3dea217
commit b41b9de905
1 changed files with 3 additions and 2 deletions
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5
artiq/gateware/targets/kc705.py
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@ -458,6 +458,7 @@ class AD9154JESD(Module, AutoCSR):
Instance("BUFG", i_I=self.refclk, o_O=self.cd_jesd.clk), Instance("BUFG", i_I=self.refclk, o_O=self.cd_jesd.clk),
AsyncResetSynchronizer(self.cd_jesd, ResetSignal("rio_phy")), AsyncResetSynchronizer(self.cd_jesd, ResetSignal("rio_phy")),
] ]
platform.add_period_constraint(self.cd_jesd.clk, 1e9/refclk_freq)
qpll = GTXQuadPLL(self.refclk, refclk_freq, linerate) qpll = GTXQuadPLL(self.refclk, refclk_freq, linerate)
self.submodules += qpll self.submodules += qpll
@ -467,8 +468,8 @@ class AD9154JESD(Module, AutoCSR):
qpll, platform.request("ad9154_jesd", i), fabric_freq) qpll, platform.request("ad9154_jesd", i), fabric_freq)
platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate) platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
self.comb += phy.gtx.gtx_init.bypass_phalign.eq(1) # TODO self.comb += phy.gtx.gtx_init.bypass_phalign.eq(1) # TODO
for clk in self.cd_jesd.clk, refclk_pads.p, self.refclk: platform.add_false_path_constraints(self.cd_jesd.clk,
platform.add_false_path_constraints(clk, phy.gtx.cd_tx.clk) phy.gtx.cd_tx.clk)
phys.append(phy) phys.append(phy)
to_jesd = ClockDomainsRenamer("jesd") to_jesd = ClockDomainsRenamer("jesd")
self.submodules.core = to_jesd(JESD204BCoreTX(phys, settings, self.submodules.core = to_jesd(JESD204BCoreTX(phys, settings,