gateware: soc -> amp.soc

artiq/gateware/amp/__init__.py

@@ -1,2 +1 @@
-from artiq.gateware.amp.kernel_cpu import KernelCPU
-from artiq.gateware.amp.mailbox import Mailbox
+from artiq.gateware.amp.soc import AMPSoC

artiq/gateware/amp/soc.py

@@ -5,7 +5,8 @@ from misoc.cores import timer
 from misoc.interconnect import wishbone
 from misoc.integration.builder import *
 
-from artiq.gateware import amp
+from artiq.gateware.amp.kernel_cpu import KernelCPU
+from artiq.gateware.amp.mailbox import Mailbox
 from artiq import __artiq_dir__ as artiq_dir
 
 
@@ -18,11 +19,11 @@ class AMPSoC:
         if not hasattr(self, "cpu"):
             raise ValueError("Platform SoC must be initialized first")
 
-        self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
+        self.submodules.kernel_cpu = KernelCPU(self.platform)
         self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
         self.csr_devices.append("kernel_cpu")
 
-        self.submodules.mailbox = amp.Mailbox(size=3)
+        self.submodules.mailbox = Mailbox(size=3)
         self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
                           self.mailbox.i1)
         self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),

artiq/gateware/targets/kc705_dds.py

@@ -14,7 +14,7 @@ from misoc.cores import gpio
 from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
 from misoc.integration.builder import builder_args, builder_argdict
 
-from artiq.gateware.soc import AMPSoC, build_artiq_soc
+from artiq.gateware.amp import AMPSoC, build_artiq_soc
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
                                      dds, spi)

artiq/gateware/targets/kc705_drtio_master.py

@@ -10,7 +10,7 @@ from misoc.integration.soc_core import mem_decoder
 from misoc.integration.builder import builder_args, builder_argdict
 
 from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
-from artiq.gateware.soc import AMPSoC, build_artiq_soc
+from artiq.gateware.amp import AMPSoC, build_artiq_soc
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple
 from artiq.gateware.drtio.transceiver import gtx_7series

artiq/gateware/targets/phaser.py

@@ -21,7 +21,7 @@ from misoc.cores import spi as spi_csr
 from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
 from misoc.integration.builder import builder_args, builder_argdict
 
-from artiq.gateware.soc import AMPSoC, build_artiq_soc
+from artiq.gateware.amp import AMPSoC, build_artiq_soc
 from artiq.gateware import rtio
 from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
 from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,

artiq/gateware/targets/pipistrello.py

@@ -17,7 +17,7 @@ from misoc.targets.pipistrello import (BaseSoC, soc_pipistrello_args,
                                        soc_pipistrello_argdict)
 from misoc.integration.builder import builder_args, builder_argdict
 
-from artiq.gateware.soc import AMPSoC, build_artiq_soc
+from artiq.gateware.amp import AMPSoC, build_artiq_soc
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi
 from artiq import __version__ as artiq_version