forked from M-Labs/artiq
drtio: forward clocks to SMA connectors for debugging
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9c646801e3
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@ -78,6 +78,11 @@ class Master(MiniSoC, AMPSoC):
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self.drtio.aux_controller.bus)
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self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
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platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
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]
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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@ -98,6 +98,11 @@ class Satellite(BaseSoC):
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
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platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
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]
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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