forked from M-Labs/artiq
add variant in identifier string
Also add without-sawg suffixes on Sayma. Closes #1060 Closes #1059
This commit is contained in:
parent
b6c70b3cb0
commit
b27fa8964b
@ -1,12 +1,36 @@
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import os
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import subprocess
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from misoc.cores import identifier
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from misoc.integration.builder import *
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from artiq.gateware.amp import AMPSoC
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from artiq import __version__ as artiq_version
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from artiq import __artiq_dir__ as artiq_dir
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__all__ = ["add_identifier", "build_artiq_soc"]
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def get_identifier_string(soc, suffix="", add_class_name=True):
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r = artiq_version
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if suffix or add_class_name:
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r += ";"
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if add_class_name:
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r += soc.__class__.__name__.lower()
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r += suffix
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return r
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def add_identifier(soc, *args, **kwargs):
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if hasattr(soc, "identifier"):
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raise ValueError
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identifier_str = get_identifier_string(soc, *args, **kwargs)
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soc.submodules.identifier = identifier.Identifier(identifier_str)
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soc.config["IDENTIFIER_STR"] = identifier_str
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def build_artiq_soc(soc, argdict):
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firmware_dir = os.path.join(artiq_dir, "firmware")
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builder = Builder(soc, **argdict)
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@ -220,7 +220,7 @@ class CommKernel:
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raise UnsupportedDevice("Unsupported runtime ID: {}"
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.format(runtime_id))
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gateware_version = self._read_string()
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gateware_version = self._read_string().split(";")[0]
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if gateware_version != software_version and not self.warned_of_mismatch:
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logger.warning("Mismatch between gateware (%s) "
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"and software (%s) versions",
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10
artiq/firmware/Cargo.lock
generated
10
artiq/firmware/Cargo.lock
generated
@ -13,7 +13,6 @@ version = "0.0.0"
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dependencies = [
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"bitflags 1.0.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"board_misoc 0.0.0",
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"build_artiq 0.0.0",
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"build_misoc 0.0.0",
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"byteorder 1.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"crc 1.8.1 (registry+https://github.com/rust-lang/crates.io-index)",
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@ -47,13 +46,6 @@ dependencies = [
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"smoltcp 0.4.0 (git+https://github.com/m-labs/smoltcp?rev=181083f)",
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]
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[[package]]
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name = "build_artiq"
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version = "0.0.0"
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dependencies = [
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"walkdir 1.0.7 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "build_const"
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version = "0.2.1"
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@ -224,7 +216,6 @@ dependencies = [
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"alloc_list 0.0.0",
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"board_artiq 0.0.0",
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"board_misoc 0.0.0",
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"build_artiq 0.0.0",
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"build_misoc 0.0.0",
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"byteorder 1.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"cslice 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
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@ -255,7 +246,6 @@ version = "0.0.0"
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dependencies = [
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"board_artiq 0.0.0",
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"board_misoc 0.0.0",
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"build_artiq 0.0.0",
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"build_misoc 0.0.0",
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"log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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@ -10,7 +10,6 @@ path = "lib.rs"
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[build-dependencies]
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build_misoc = { path = "../libbuild_misoc" }
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build_artiq = { path = "../libbuild_artiq" }
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[dependencies]
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failure = { version = "0.1", default-features = false }
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@ -1,11 +0,0 @@
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[package]
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authors = ["M-Labs"]
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name = "build_artiq"
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version = "0.0.0"
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[lib]
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name = "build_artiq"
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path = "lib.rs"
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[dependencies]
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walkdir = "1.0"
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@ -1,45 +0,0 @@
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extern crate walkdir;
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use std::env;
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use std::fs;
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use std::path::Path;
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use std::process::Command;
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use walkdir::WalkDir;
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pub fn git_describe() {
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let git_checkout = Path::new("../../..");
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for entry in WalkDir::new(git_checkout) {
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let entry = entry.unwrap();
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println!("cargo:rerun-if-changed={}", entry.path().display());
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}
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let version;
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if git_checkout.join(".git").exists() {
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let git_describe =
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Command::new("git")
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.arg("describe")
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.arg("--tags")
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.arg("--dirty")
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.arg("--always")
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.arg("--long")
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.arg("--abbrev=8")
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.output()
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.ok()
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.and_then(|o| String::from_utf8(o.stdout).ok())
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.map(|mut s| {
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let len = s.trim_right().len();
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s.truncate(len);
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s
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})
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.unwrap();
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let parts = git_describe.split("-").collect::<Vec<_>>();
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version = format!("{}+{}.{}", parts[0], parts[1], parts[2]);
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} else {
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version = "unknown".to_owned();
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}
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let out_dir = env::var("OUT_DIR").unwrap();
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let git_describe = Path::new(&out_dir).join("git-describe");
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fs::write(&git_describe, version).unwrap();
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}
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@ -11,7 +11,6 @@ path = "main.rs"
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[build-dependencies]
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build_misoc = { path = "../libbuild_misoc" }
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build_artiq = { path = "../libbuild_artiq" }
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[dependencies]
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failure = { version = "0.1", default-features = false }
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@ -1,7 +1,5 @@
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extern crate build_misoc;
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extern crate build_artiq;
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fn main() {
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build_misoc::cfg();
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build_artiq::git_describe();
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}
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@ -66,7 +66,7 @@ fn startup() {
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irq::set_ie(true);
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clock::init();
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info!("ARTIQ runtime starting...");
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info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
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info!("software version {}", csr::CONFIG_IDENTIFIER_STR);
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info!("gateware version {}", ident::read(&mut [0; 64]));
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match config::read_str("log_level", |r| r.map(|s| s.parse())) {
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@ -355,8 +355,7 @@ pub extern fn panic_fmt(args: core::fmt::Arguments, file: &'static str,
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println!("panic at {}:{}:{}: {}", file, line, column, args);
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println!("backtrace for software version {}:",
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include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
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println!("backtrace for software version {}:", csr::CONFIG_IDENTIFIER_STR);
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let _ = unwind_backtrace::backtrace(|ip| {
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// Backtrace gives us the return address, i.e. the address after the delay slot,
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// but we're interested in the call instruction.
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@ -11,7 +11,6 @@ path = "main.rs"
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[build-dependencies]
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build_misoc = { path = "../libbuild_misoc" }
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build_artiq = { path = "../libbuild_artiq" }
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[dependencies]
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log = { version = "0.4", default-features = false }
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@ -1,7 +1,5 @@
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extern crate build_misoc;
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extern crate build_artiq;
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fn main() {
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build_misoc::cfg();
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build_artiq::git_describe();
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}
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@ -260,7 +260,7 @@ pub extern fn main() -> i32 {
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uart_logger::ConsoleLogger::register();
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info!("ARTIQ satellite manager starting...");
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info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
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info!("software version {}", csr::CONFIG_IDENTIFIER_STR);
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info!("gateware version {}", ident::read(&mut [0; 64]));
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#[cfg(has_slave_fpga_cfg)]
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@ -22,8 +22,7 @@ from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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from artiq.build_soc import *
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class _RTIOCRG(Module, AutoCSR):
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@ -100,11 +99,11 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self)
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self.submodules.leds = gpio.GPIOOut(Cat(
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self.platform.request("user_led", 0)))
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@ -622,11 +621,11 @@ class _MasterBase(MiniSoC, AMPSoC):
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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@ -754,8 +753,8 @@ class _SatelliteBase(BaseSoC):
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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add_identifier(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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@ -18,8 +18,7 @@ from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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dds, spi2, ad53xx_monitor)
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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from artiq.build_soc import *
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class _RTIOCRG(Module, AutoCSR):
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@ -219,11 +218,12 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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@ -22,8 +22,7 @@ from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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from artiq.build_soc import *
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class AD9154(Module, AutoCSR):
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@ -132,12 +131,12 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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RTMCommon.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "100"
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platform = self.platform
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@ -238,12 +237,12 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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RTMCommon.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "100"
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platform = self.platform
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@ -385,11 +384,11 @@ class Master(MiniSoC, AMPSoC):
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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@ -504,9 +503,9 @@ class Satellite(BaseSoC, RTMCommon):
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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RTMCommon.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "150"
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platform = self.platform
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