forked from M-Labs/artiq
sawg: unittest data format
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2f838e3512
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@ -26,7 +26,7 @@ class Spline:
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@portable(flags=["fast-math"])
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def to_mu64(self, value: TFloat) -> TList(TInt32):
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v = int(round(value*self.scale), width=64)
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return [int(v >> 32, width=32), int(v, width=32)]
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return [int(v, width=32), int(v >> 32, width=32)]
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@kernel
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def set_mu(self, value: TInt32):
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@ -73,7 +73,6 @@ class Spline:
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wi = (vi >> k) & 0xffff
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v[j//2] += wi << (16 * ((j + 1)//2 - j//2))
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j += 1
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v.append(vi)
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return v
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@kernel
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@ -0,0 +1,141 @@
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import unittest
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import numpy as np
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import migen as mg
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from artiq.coredevice import sawg
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from artiq.language import delay_mu, core as core_language
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from artiq.gateware.rtio.phy.sawg import Channel
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from artiq.sim import devices as sim_devices, time as sim_time
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class RTIOManager:
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def __init__(self):
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self.outputs = []
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def rtio_output(self, now, channel, addr, data):
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self.outputs.append((now, channel, addr, data))
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def rtio_output_list(self, *args, **kwargs):
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self.rtio_output(*args, **kwargs)
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def int(self, value, width=32):
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if width == 32:
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return np.int32(value)
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elif width == 64:
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return np.int64(value)
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else:
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raise ValueError(width)
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def patch(self, mod):
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assert not getattr(mod, "_saved", None)
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mod._saved = {}
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for name in "rtio_output rtio_output_list int".split():
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mod._saved[name] = getattr(mod, name, None)
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setattr(mod, name, getattr(self, name))
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def unpatch(self, mod):
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mod.__dict__.update(mod._saved)
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del mod._saved
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class SAWGTest(unittest.TestCase):
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def setUp(self):
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core_language.set_time_manager(sim_time.Manager())
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self.rtio_manager = RTIOManager()
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self.rtio_manager.patch(sawg)
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self.core = sim_devices.Core({})
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self.core.coarse_ref_period = 8
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self.channel = mg.ClockDomainsRenamer({"rio_phy": "sys"})(
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Channel(width=16, parallelism=4))
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self.driver = sawg.SAWG({"core": self.core}, channel_base=0,
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parallelism=self.channel.parallelism)
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def tearDown(self):
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self.rtio_manager.unpatch(sawg)
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def test_instantiate(self):
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pass
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def test_make_events(self):
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d = self.driver
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d.offset.set(.9)
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delay_mu(2*8)
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d.frequency0.set64(.1)
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delay_mu(2*8)
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d.offset.set(0)
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self.assertEqual(
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self.rtio_manager.outputs, [
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(0, 1, 0, int(round(
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(1 << self.driver.offset.width - 1)*.9))),
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(2*8, 8, 0, [0, int(round(
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(1 << self.driver.frequency0.width - 1) *
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self.channel.parallelism*.1))]),
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(4*8, 1, 0, 0),
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])
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def run_channel(self, events):
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def gen(dut, events):
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c = 0
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for time, channel, address, data in events:
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assert c <= time
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while c < time:
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yield
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c += 1
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for phy in dut.phys:
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yield phy.rtlink.o.stb.eq(0)
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rt = dut.phys[channel].rtlink.o
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if isinstance(data, list):
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data = sum(d << i*32 for i, d in enumerate(data))
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yield rt.data.eq(int(data))
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yield rt.stb.eq(1)
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assert not (yield rt.busy)
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def log(dut, data, n):
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for i in range(dut.latency):
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yield
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for i in range(n):
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yield
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data.append((yield from [(yield _) for _ in dut.o]))
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data = []
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mg.run_simulation(self.channel, [
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gen(self.channel, events),
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log(self.channel, data, int(events[-1][0]//8) + 1)],
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vcd_name="dds.vcd")
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return sum(data, [])
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def test_channel(self):
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self.test_make_events()
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out = self.run_channel(self.rtio_manager.outputs)
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print(out)
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def test_coeff(self):
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import struct
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for v in [-.1], [.1, -.01], [.1, .01, -.00001], \
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[.1, .01, .00001, -.000000001]:
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ch = self.driver.offset
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p = ch.coeff_to_mu(v)
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t = ch.time_width
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w = ch.width
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p0 = [struct.pack("<" + "_hiqq"[(w + i*t)//16],
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int(round(vi*ch.scale*ch.time_scale**i))
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)[:(w + i*t)//8]
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for i, vi in enumerate(v)]
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p0 = b"".join(p0)
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if len(p0) % 4:
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p0 += b"\x00"*(4 - len(p0) % 4)
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p0 = list(struct.unpack("<" + "I"*((len(p0) + 3)//4), p0))
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with self.subTest(v):
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self.assertEqual(p, p0)
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def test_linear(self):
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d = self.driver
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d.offset.set_list_mu([100, 10])
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delay_mu(10*8)
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d.offset.set_list([0])
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delay_mu(1*8)
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out = self.run_channel(self.rtio_manager.outputs)
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self.assertEqual(
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out, sum(([100 + i*10]*self.channel.parallelism
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for i in range(11)), []))
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