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firmware/libboard: use correct jesd clocking

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This commit is contained in:
Florent Kermarrec 2017-11-10 10:56:45 +01:00
parent d90d624877
commit aff1609a53
3 changed files with 33 additions and 16 deletions
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4
artiq/firmware/libboard/build.rs
View File

@ -8,12 +8,12 @@ use std::process::Command;
fn gen_hmc7043_writes() {
println!("cargo:rerun-if-changed=hmc7043_gen_writes.py");
println!("cargo:rerun-if-changed=hmc7043_guiexport_10gbps.py");
println!("cargo:rerun-if-changed=hmc7043_guiexport_6gbps.py");
let hmc7043_writes =
Command::new("python3")
.arg("hmc7043_gen_writes.py")
.arg("hmc7043_guiexport_10gbps.py")
.arg("hmc7043_guiexport_6gbps.py")
.output()
.ok()
.and_then(|o| String::from_utf8(o.stdout).ok())

7
artiq/firmware/libboard/hmc7043_guiexport_10gbps.py → artiq/firmware/libboard/hmc7043_guiexport_6gbps.py
View File

@ -315,14 +315,14 @@ dut.write(0xED, 0x0)
# clkgrp2_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0xEE, 0x9)
# clkgrp3_div1_cfg1_en[0:0] = 0x0
# clkgrp3_div1_cfg1_en[0:0] = 0x1
# clkgrp3_div1_cfg1_phdelta_mslip[1:1] = 0x1
# clkgrp3_div1_cfg2_startmode[3:2] = 0x0
# clkgrp3_div1_cfg1_rev[4:4] = 0x1
# clkgrp3_div1_cfg1_slipmask[5:5] = 0x1
# clkgrp3_div1_cfg1_reseedmask[6:6] = 0x1
# clkgrp3_div1_cfg1_hi_perf[7:7] = 0x0
dut.write(0xF0, 0x72)
dut.write(0xF0, 0x73)
# clkgrp3_div1_cfg12_divrat_lsb[7:0] = 0x2
dut.write(0xF1, 0x2)
@ -693,5 +693,4 @@ dut.write(0x151, 0x0)
# clkgrp7_div2_cfg5_drvr_mode[4:3] = 0x1
# clkgrp7_div2_cfg_outbuf_dyn[5:5] = 0x0
# clkgrp7_div2_cfg2_mutesel[7:6] = 0x0
dut.write(0x152, 0xB)
dut.write(0x152, 0xB)

38
artiq/firmware/libboard/hmc830_7043.rs
View File

@ -1,15 +1,32 @@
/*
* HMC830 config:
* 100MHz input, 1GHz output
* 100MHz input, 1.2GHz output
* fvco = (refclk / r_divider) * n_divider
* fout = fvco/2
*
* HMC7043 config:
* dac clock: 1GHz (div=1)
* fpga clock: 250MHz (div=4)
* sysref clock: 15.625MHz (div=64)
* dac clock: 600MHz (div=1)
* fpga clock: 150MHz (div=4)
* sysref clock: 9.375MHz (div=64)
*/
mod clock_mux {
use csr;
const CLK_SRC_EXT_SEL : u8 = 1 << 0;
const REF_CLK_SRC_SEL : u8 = 1 << 1;
const DAC_CLK_SRC_SEL : u8 = 1 << 2;
pub fn init() -> Result<(), &'static str> {
unsafe {
csr::clock_mux::out_write(
1*CLK_SRC_EXT_SEL | // use ext clk from sma
1*REF_CLK_SRC_SEL | //
0*DAC_CLK_SRC_SEL); // use clk from dac_clk // FIXME (should use hmc830 output)
}
Ok(())
}
}
mod hmc830 {
use clock;
@ -31,7 +48,7 @@ mod hmc830 {
(0xa, 0x2046),
(0xb, 0x7c061),
(0xf, 0x81),
(0x3, 0x28), // n_divider
(0x3, 0x30), // n_divider
];
fn spi_setup() {
@ -90,11 +107,11 @@ mod hmc830 {
let t = clock::get_ms();
info!("HMC830 waiting for lock...");
//while read(0x12) & 0x02 == 0 {
// if clock::get_ms() > t + 2000 {
// return Err("HMC830 lock timeout");
// }
//}
while read(0x12) & 0x02 == 0 {
if clock::get_ms() > t + 2000 {
return Err("HMC830 lock timeout");
}
}
Ok(())
}
@ -163,6 +180,7 @@ mod hmc7043 {
}
pub fn init() -> Result<(), &'static str> {
clock_mux::init();
hmc830::init()?;
hmc7043::init()
}