forked from M-Labs/artiq
clean up hmc7043 reset
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988054f4bb
commit
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@ -229,7 +229,7 @@ pub mod hmc7043 {
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info!("enabling hmc7043");
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unsafe {
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csr::crg::hmc7043_rst_write(0);
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csr::hmc7043_reset::out_write(0);
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}
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spi_setup();
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@ -19,11 +19,8 @@ from artiq.gateware import serwb
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from artiq import __version__ as artiq_version
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class CRG(Module, AutoCSR):
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class CRG(Module):
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def __init__(self, platform):
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self.hmc7043_rst = CSRStorage(reset=1)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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@ -113,7 +110,6 @@ class SaymaRTM(Module):
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csr_devices = []
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self.submodules.crg = CRG(platform)
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csr_devices.append("crg")
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clk_freq = 125e6
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@ -179,7 +175,9 @@ class SaymaRTM(Module):
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platform.request("ad9154_spi", 0),
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platform.request("ad9154_spi", 1)))
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csr_devices.append("converter_spi")
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self.comb += platform.request("hmc7043_reset").eq(self.crg.hmc7043_rst.storage)
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self.submodules.hmc7043_reset = gpio.GPIOOut(
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platform.request("hmc7043_reset"), reset_out=1)
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csr_devices.append("hmc7043_reset")
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# AMC/RTM serwb
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serwb_pads = platform.request("amc_rtm_serwb")
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@ -15,7 +15,7 @@ requirements:
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- python >=3.5.3,<3.6
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- setuptools 33.1.1
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- migen 0.7 py35_35+git9bc084a
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- misoc 0.11 py35_15+git7f63aff5
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- misoc 0.11 py35_18+gitfb92c5ee
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- jesd204b 0.6
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- microscope
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- binutils-or1k-linux >=2.27
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