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simplify dt reset

This commit is contained in:
Robert Jördens 2022-09-08 08:39:48 +02:00
parent 4df880faf6
commit af28bf3550
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/rtio/phy/phaser.py
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@ -111,11 +111,11 @@ class MiqroChannel(Module):
dt.eq(dt + 2), dt.eq(dt + 2),
), ),
If(self.ack, If(self.ack,
dt.eq(0), dt[1:].eq(0),
stb.eq(0),
If(stb, If(stb,
[r.eq(0) for r in regs], [r.eq(0) for r in regs],
), ),
stb.eq(0),
), ),
If(self.rtlink.o.stb, If(self.rtlink.o.stb,
Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data), Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data),