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miqro: docs
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@ -47,7 +47,7 @@ PHASER_ADDR_SERVO_CFG1 = 0x31
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# 0x32 - 0x71 servo coefficients + offset data
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PHASER_ADDR_SERVO_DATA_BASE = 0x32
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# 0x78 Miqro channel profile/window memories
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# 0x72 - 0x78 Miqro channel profile/window memories
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PHASER_ADDR_MIQRO_MEM_ADDR = 0x72
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PHASER_ADDR_MIQRO_MEM_DATA = 0x74
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@ -84,6 +84,19 @@ class Phaser:
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Phaser contains a 4 channel, 1 GS/s DAC chip with integrated upconversion,
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quadrature modulation compensation and interpolation features.
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The coredevice RTIO PHY and the Phaser gateware come in different modes
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that have different features. Phaser mode and coredevice PHY are both
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both selected at gateware compile-time and need to match.
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Phaser gateware | Coredevice PHY | Features per :class:`PhaserChannel`
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--------------- | -------------- | -----------------------------------
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Base <= v0.5 | Base | Base (5 :class:`PhaserOscillator`)
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Base >= v0.6 | Base | Base + Servo
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Miqro >= v0.6 | Miqro | :class:`Miqro`
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Base mode
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---------
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The coredevice produces 2 IQ (in-phase and quadrature) data streams with 25
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MS/s and 14 bit per quadrature. Each data stream supports 5 independent
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numerically controlled IQ oscillators (NCOs, DDSs with 32 bit frequency, 16
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@ -114,6 +127,16 @@ class Phaser:
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absolute phase with respect to other RTIO input and output events
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(see `get_next_frame_mu()`).
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Miqro mode
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----------
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See :class:`Miqro`
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Here the DAC operates in 4x interpolation.
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Analog flow
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-----------
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The four analog DAC outputs are passed through anti-aliasing filters.
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In the baseband variant, the even/in-phase DAC channels feed 31.5 dB range
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@ -131,6 +154,9 @@ class Phaser:
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configured through a shared SPI bus that is accessed and controlled via
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FPGA registers.
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Servo
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-----
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Each phaser output channel features a servo to control the RF output amplitude
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using feedback from an ADC. The servo consists of a first order IIR (infinite
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impulse response) filter fed by the ADC and a multiplier that scales the I
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@ -1290,90 +1316,98 @@ class Miqro:
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"""
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Miqro pulse generator.
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Notes
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-----
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* The annotation that some operation is "expensive" does not mean it is impossible, just
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that it may take a significant amount of time and resources to execute such that
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it may be impractical when used often or during fast pulse sequences.
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They are intended for use in calibration and initialization.
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A Miqro instance represents one RF output. The DSP components are fully
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contained in the Phaser gateware. The output is generated by with
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the following data flow:
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Functionality
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-------------
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A Miqro instance represents one RF output.
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The output is generated by with the following data flow:
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Oscillators
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...........
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### Oscillators
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* There are n_osc = 16 oscillators with oscillator IDs 0..n_osc-1.
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* Each oscillator outputs one tone at any given time
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I/Q (quadrature, a.k.a. complex) 2x16 bit signed data
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at tau = 4 ns sample intervals, 250 MS/s, Nyquist 125 MHz, bandwidth 200 MHz
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(from f = -100..+100 MHz, taking into account the interpolation anti-aliasing
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filters in subsequent interpolators),
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32 bit frequency (f) resolution (~ 1/16 Hz),
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16 bit unsigned amplitude (a) resolution
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16 bit phase (p) resolution
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* I/Q (quadrature, a.k.a. complex) 2x16 bit signed data
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at tau = 4 ns sample intervals, 250 MS/s, Nyquist 125 MHz, bandwidth 200 MHz
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(from f = -100..+100 MHz, taking into account the interpolation anti-aliasing
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filters in subsequent interpolators),
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* 32 bit frequency (f) resolution (~ 1/16 Hz),
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* 16 bit unsigned amplitude (a) resolution
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* 16 bit phase offset (p) resolution
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* The output phase p' of each oscillator at time t (boot/reset/initialization of the
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device at t=0) is then p' = f*t + p (mod 1 turn) where f and p are the
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(currently active) profile frequency and phase.
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The terms "phase coherent" and "phase tracking" are defined to refer to this
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choice of oscillator output phase p'.
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Note that the phase p is not accumulated (on top of previous
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phases, previous profiles, or oscillator history). It is "absolute" in the
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sense that frequency f and phase p fully determine oscillator
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output phase p' at time t. This is unlike typical DDS behavior.
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device at t=0) is then p' = f*t + p (mod 1 turn) where f and p are the (currently
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active) profile frequency and phase offset.
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* Note: The terms "phase coherent" and "phase tracking" are defined to refer to this
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choice of oscillator output phase p'. Note that the phase offset p is not relative to
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(on top of previous phase/profiles/oscillator history).
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It is "absolute" in the sense that frequency f and phase offset p fully determine
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oscillator output phase p' at time t. This is unlike typical DDS behavior.
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* Frequency, phase, and amplitude of each oscillator are configurable by selecting one of
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n_profile = 32 profiles 0..n_profile-1. This selection is fast and can be done for
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each pulse. The phase coherence defined above is guaranteed for each
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profile individually.
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n_profile = 32 profiles 0..n_profile-1. This selection is fast and can be done for
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each pulse. The phase coherence defined above is guaranteed for each
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profile individually.
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* Note: one profile per oscillator (usually profile index 0) should be reserved
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for the NOP (no operation, identity) profile, usually with zero
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amplitude.
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for the NOP (no operation, identity) profile, usually with zero amplitude.
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* Data for each profile for each oscillator can be configured
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individually. Storing profile data should be considered "expensive".
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individually. Storing profile data should be considered "expensive".
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* Note: The annotation that some operation is "expensive" does not mean it is
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impossible, just that it may take a significant amount of time and
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resources to execute such that it may be impractical when used often or
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during fast pulse sequences. They are intended for use in calibration and
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initialization.
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Summation
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.........
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### Summation
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* The oscillator outputs are added together (wrapping addition).
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* The user must ensure that the sum of oscillators outputs does
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not exceed the (16 bit signed) data range. In general that means that the sum of the
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amplitudes must not exceed the range.
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* The user must ensure that the sum of oscillators outputs does not exceed the
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data range. In general that means that the sum of the amplitudes must not
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exceed one.
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### Shaper
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* The summed output stream is then multiplied with a the complex-valued output of a
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triggerable shaper.
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* Triggering the shaper corresponds to passing a pulse from all
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oscillators to the RF output.
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* Selected profiles become active simultaneously
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(on the same output sample) when triggering the shaper.
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* The shaper reads (replays) window samples from a memory of size n_window = 1 << 10 starting
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and stopping at memory locations specified.
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* Each window memory segment starts with a header determining segment
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length and interpolation parameters.
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* The window samples are interpolated by a factor (rate change)
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between 1 and r = 1 << 12.
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* The interpolation order is constant, linear, quadratic, or cubic. This
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corresponds to interpolation modes from rectangular window (1st order CIC)
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or zero order hold) and to Parzen window (4th order CIC, cubic spline).
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* This results in support for pulse lengths of between tau and a bit more than
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r * n_window * tau = (1 << 12 + 10) tau ~ 17 ms.
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* Windows can be configured to be head-less and/or tail-less, meaning, they
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do not feed zero-amplitude samples into the shaper before and after
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each window. This is used to implement pulses with arbitrary length or
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CW output.
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Shaper
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......
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* The summed complex output stream is then multiplied with a the complex-valued
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output of a triggerable shaper.
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* Triggering the shaper corresponds to passing a pulse from all oscillators to
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the RF output.
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* Selected profiles become active simultaneously (on the same output sample) when
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triggering the shaper with the first shaper output sample.
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* The shaper reads (replays) window samples from a memory of size n_window = 1 << 10.
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* The window memory can be segmented by choosing different start indices
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to support different windows.
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to support different windows.
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* Each window memory segment starts with a header determining segment
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length and interpolation parameters.
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* The window samples are interpolated by a factor (rate change) between 1 and
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r = 1 << 12.
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* The interpolation order is constant, linear, quadratic, or cubic. This
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corresponds to interpolation modes from rectangular window (1st order CIC)
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or zero order hold) to Parzen window (4th order CIC or cubic spline).
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* This results in support for single shot pulse lengths (envelope support) between
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tau and a bit more than r * n_window * tau = (1 << 12 + 10) tau ~ 17 ms.
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* Windows can be configured to be head-less and/or tail-less, meaning, they
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do not feed zero-amplitude samples into the shaper before and after
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each window respectively. This is used to implement pulses with arbitrary
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length or CW output.
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Overall properties
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..................
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### Overall properties
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* The DAC may upconvert the signal by applying a frequency offset f1 with
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phase p1.
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phase p1.
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* In the Upconverter Phaser variant, the analog quadrature upconverter
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applies another frequency of f2 and phase p2.
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* The resulting phase of the signal at the SMA output is
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(f + f1 + f2)*t + p + s(t - t0) + p1 + p2 (mod 1 turn)
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where s(t - t0) is the phase of the interpolated
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shaper output, and t0 is the trigger time (fiducial of the shaper).
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Unsurprisingly the frequency is the derivative of the phase.
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applies another frequency of f2 and phase p2.
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* The resulting phase of the signal from one oscillator at the SMA output is
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(f + f1 + f2)*t + p + s(t - t0) + p1 + p2 (mod 1 turn)
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where s(t - t0) is the phase of the interpolated
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shaper output, and t0 is the trigger time (fiducial of the shaper).
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Unsurprisingly the frequency is the derivative of the phase.
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* Group delays between pulse parameter updates are matched across oscillators,
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shapers, and channels.
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* The minimum time to change profiles and phase offsets is ~128 ns (estimate, TBC).
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This is the minimum pulse interval.
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This is the minimum pulse interval.
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The sustained pulse rate of the RTIO PHY/Fastlink is one pulse per Fastlink frame
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(may be increased, TBC).
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"""
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def __init__(self, channel):
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@ -1458,7 +1492,7 @@ class Miqro:
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for iqi in iq
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]
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self.set_window_mu(start, iq_mu, rate, shift, order, head, tail)
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return rate
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return rate*4*ns
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@kernel
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def encode(self, window, profiles, data):
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