forked from M-Labs/artiq
rtlink: sanity-check parameters
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@ -8,6 +8,10 @@ class OInterface:
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self.stb = Signal()
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self.busy = Signal()
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assert 0 <= data_width <= 512
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assert 0 <= address_width <= 8
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assert 0 <= fine_ts_width <= 4
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if data_width:
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self.data = Signal(data_width, reset_less=True)
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if address_width:
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@ -35,6 +39,9 @@ class IInterface:
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timestamped=True, fine_ts_width=0, delay=0):
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self.stb = Signal()
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assert 0 <= data_width <= 32
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assert 0 <= fine_ts_width <= 4
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if data_width:
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self.data = Signal(data_width, reset_less=True)
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if fine_ts_width:
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