forked from M-Labs/artiq
drtio/gth_ultrascale: support OBUFDS_GTE3
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fe0c324b38
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@ -37,6 +37,8 @@ class GTHSingle(Module):
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self.rx_ready = Signal()
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self.rx_ready = Signal()
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# transceiver direct clock outputs
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# transceiver direct clock outputs
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# for OBUFDS_GTE3
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self.rxrecclkout = Signal()
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# useful to specify clock constraints in a way palatable to Vivado
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# useful to specify clock constraints in a way palatable to Vivado
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self.txoutclk = Signal()
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self.txoutclk = Signal()
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self.rxoutclk = Signal()
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self.rxoutclk = Signal()
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@ -521,6 +523,7 @@ class GTHSingle(Module):
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i_RXSYSCLKSEL=0b00,
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i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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i_RXOUTCLKSEL=0b010,
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i_RXPLLCLKSEL=0b00,
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i_RXPLLCLKSEL=0b00,
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o_RXRECCLKOUT=self.rxrecclkout,
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o_RXOUTCLK=self.rxoutclk,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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i_RXUSRCLK2=ClockSignal("rtio_rx"),
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i_RXUSRCLK2=ClockSignal("rtio_rx"),
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@ -633,7 +636,7 @@ class GTHTXPhaseAlignement(Module):
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class GTH(Module, TransceiverInterface):
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class GTH(Module, TransceiverInterface):
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def __init__(self, clock_pads, data_pads, sys_clk_freq, rtio_clk_freq, rtiox_mul=2, dw=20, master=0):
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def __init__(self, clock_pads, data_pads, sys_clk_freq, rtio_clk_freq, rtiox_mul=2, dw=20, master=0, clock_recout_pads=None):
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self.nchannels = nchannels = len(data_pads)
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self.nchannels = nchannels = len(data_pads)
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self.gths = []
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self.gths = []
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@ -689,3 +692,9 @@ class GTH(Module, TransceiverInterface):
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getattr(self, "cd_rtio_rx" + str(i)).clk.eq(self.gths[i].cd_rtio_rx.clk),
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getattr(self, "cd_rtio_rx" + str(i)).clk.eq(self.gths[i].cd_rtio_rx.clk),
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getattr(self, "cd_rtio_rx" + str(i)).rst.eq(self.gths[i].cd_rtio_rx.rst)
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getattr(self, "cd_rtio_rx" + str(i)).rst.eq(self.gths[i].cd_rtio_rx.rst)
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]
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]
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if clock_recout_pads is not None:
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self.specials += Instance("OBUFDS_GTE3",
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i_I=self.gths[0].rxrecclkout,
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i_CEB=0,
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o_O=clock_recout_pads.p, o_OB=clock_recout_pads.n)
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