From ad34927b0a7b12e81ee33c757be5d44701f48c16 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 29 Feb 2016 11:35:49 +0100 Subject: [PATCH] spi: RTIO_SPI_CHANNEL -> RTIO_FIRST_SPI_CHANNEL --- artiq/gateware/targets/kc705.py | 2 +- artiq/gateware/targets/pipistrello.py | 2 +- artiq/runtime/spi.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 3cc948aab..42b5af981 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -259,7 +259,7 @@ class NIST_CLOCK(_NIST_Ions): phy = spi.SPIMaster(spi_pins) self.submodules += phy - self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels) + self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=4, ififo_depth=4)) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index d7e177517..ceb39d83f 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -200,7 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd spi_pins.cs_n = pmod.d[3:] phy = spi.SPIMaster(spi_pins) self.submodules += phy - self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels) + self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=4, ififo_depth=4)) diff --git a/artiq/runtime/spi.c b/artiq/runtime/spi.c index a72e3a4f8..20d694454 100644 --- a/artiq/runtime/spi.c +++ b/artiq/runtime/spi.c @@ -12,7 +12,7 @@ void spi_write(long long int timestamp, int channel, int addr, unsigned int data) { - rtio_chan_sel_write(CONFIG_RTIO_SPI_CHANNEL + channel); + rtio_chan_sel_write(CONFIG_RTIO_FIRST_SPI_CHANNEL + channel); rtio_o_address_write(addr); rtio_o_data_write(data); rtio_o_timestamp_write(timestamp);