forked from M-Labs/artiq
libboard/ad9154: small cleanup
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@ -376,7 +376,7 @@ fn dac_setup(linerate: u64) -> Result<(), &'static str> {
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0*ad9154_reg::SYNCCLRLAST);
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clock::spin_us(1000); // ensure at least one sysref edge
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if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 {
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return Err("A9154 no sync lock");
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return Err("AD9154 no sync lock");
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}
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write(ad9154_reg::XBAR_LN_0_1,
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0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC);
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@ -478,10 +478,10 @@ pub fn init() -> Result<(), &'static str> {
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// Release the JESD clock domain reset late, as we need to
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// set up clock chips before.
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jesd_unreset();
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//for dacno in 0..csr::AD9154.len() {
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for dacno in 0..csr::AD9154.len() {
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let dacno = dacno as u8;
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debug!("setting up A9154-{} DAC...", dacno);
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debug!("setting up AD9154-{} DAC...", dacno);
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dac_cfg(dacno)?;
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}
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Ok(())
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