forked from M-Labs/artiq
phaser: 300 MHz sample rate clock/dac
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@ -7,16 +7,16 @@ Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Gen
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*Features*:
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* 4 channels
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* 500 MHz data rate per channel (KC705 limitation)
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* 4x interpolation to 2 GHz DAC sample rate
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* up to 4 channels
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* up to 500 MHz data rate per channel (KC705 limitation)
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* up to 8x interpolation to 2.4 GHz DAC sample rate
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* Real-time control over amplitude, frequency, phase of each channel through ARTIQ RTIO commands
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* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel support
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* All SPI registers and register bits exposed as human readable names
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* Parametrized JESD204B core (also capable of operation with eight lanes)
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* The code can be reconfigured. Possible example configurations are: support 2 channels at 1 GHz datarate, support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz).
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The hardware required to use the ARTIQ phaser branch is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-noise 2 GHz reference clock.
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The hardware required to use the ARTIQ phaser branch is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-noise sample rate reference clock.
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This work was supported by the Army Research Lab.
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@ -90,7 +90,7 @@ Setup
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* Refer to the ARTIQ documentation to configure an IP address and other settings for the transmitter device.
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If the board was running stock ARTIQ before, the settings will be kept.
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* A 2 GHz of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1.
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* A 300 MHz clock of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1.
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The external RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal.
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* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``. ::
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@ -113,7 +113,7 @@ Usage
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* Run ``artiq_run repository/demo.py`` for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
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for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
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* Implement your own experiments using the SAWG channels.
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* Verify clock stability between the 2 GHz reference clock and the DAC outputs.
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* Verify clock stability between the sample rate reference clock and the DAC outputs.
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* Changes to the AD9154 configuration can also be performed at runtime in experiments.
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See the example ``dac_setup.py``.
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This can e.g. be used to enable and evaluate mix mode without having to change any other code (bitstream/bios/runtime/startup_kernel).
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@ -19,10 +19,10 @@ ts = JESD204BTransportSettings(
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)
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jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_checksum = jesd_settings.get_configuration_checksum()
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# external clk=2000MHz
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# pclock=250MHz
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# deviceclock_fpga=250MHz
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# deviceclock_dac=2000MHz
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# external clk=300MHz
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# pclock=150MHz
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# deviceclock_fpga=150MHz
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# deviceclock_dac=300MHz
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class DACSetup(EnvExperiment):
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@ -123,7 +123,7 @@ class DACSetup(EnvExperiment):
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self.ad9154.dac_write(AD9154_SPI_PAGEINDX, 0x3) # A and B dual
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self.ad9154.dac_write(AD9154_INTERP_MODE, 3) # 4x
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self.ad9154.dac_write(AD9154_INTERP_MODE, 0) # 1x
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self.ad9154.dac_write(AD9154_MIX_MODE, 0)
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self.ad9154.dac_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)) # s16
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self.ad9154.dac_write(AD9154_DATAPATH_CTRL,
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@ -28,10 +28,10 @@ class StartupKernel(EnvExperiment):
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if self.ad9154.clock_read(AD9516_PART_ID) != 0x41:
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raise ValueError("AD9516 not found")
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# use clk input, dclk=clk/4
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# use clk input, dclk=clk/2
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self.ad9154.clock_write(AD9516_PFD_AND_CHARGE_PUMP, 1*AD9516_PLL_POWER_DOWN |
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0*AD9516_CHARGE_PUMP_MODE)
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self.ad9154.clock_write(AD9516_VCO_DIVIDER, 2)
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self.ad9154.clock_write(AD9516_VCO_DIVIDER, 0)
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self.ad9154.clock_write(AD9516_INPUT_CLKS, 0*AD9516_SELECT_VCO_OR_CLK |
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0*AD9516_BYPASS_VCO_DIVIDER)
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@ -47,25 +47,21 @@ class StartupKernel(EnvExperiment):
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self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
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2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
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# FPGA deviceclk, dclk/2
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self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2)
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self.ad9154.clock_write(AD9516_DIVIDER_4_0,
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(2//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES |
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(2//2-1)*AD9516_DIVIDER_0_LOW_CYCLES)
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# FPGA deviceclk, dclk/1
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self.ad9154.clock_write(AD9516_DIVIDER_4_3, 0*AD9516_DIVIDER_4_NOSYNC |
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1*AD9516_DIVIDER_4_BYPASS_1 | 1*AD9516_DIVIDER_4_BYPASS_2)
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self.ad9154.clock_write(AD9516_DIVIDER_4_4, 0*AD9516_DIVIDER_4_DCCOFF)
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self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT |
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2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY |
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0*AD9516_OUT9_SELECT_LVDS_CMOS)
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# sysref f_data*S/(K*F), dclk/32
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self.ad9154.clock_write(AD9516_DIVIDER_3_0, (32//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
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(32//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_1)
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# sysref f_data*S/(K*F), dclk/16
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self.ad9154.clock_write(AD9516_DIVIDER_3_0, (16//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_1 |
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(16//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_1)
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self.ad9154.clock_write(AD9516_DIVIDER_3_1, 0*AD9516_DIVIDER_3_PHASE_OFFSET_1 |
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0*AD9516_DIVIDER_3_PHASE_OFFSET_2)
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self.ad9154.clock_write(AD9516_DIVIDER_3_2, (2//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_2 |
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(2//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_2)
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self.ad9154.clock_write(AD9516_DIVIDER_3_3, 0*AD9516_DIVIDER_3_NOSYNC |
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0*AD9516_DIVIDER_3_BYPASS_1 | 0*AD9516_DIVIDER_3_BYPASS_2)
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0*AD9516_DIVIDER_3_BYPASS_1 | 1*AD9516_DIVIDER_3_BYPASS_2)
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self.ad9154.clock_write(AD9516_DIVIDER_3_4, 0*AD9516_DIVIDER_3_DCCOFF)
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self.ad9154.clock_write(AD9516_OUT6, 1*AD9516_OUT6_LVDS_OUTPUT_CURRENT |
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2*AD9516_OUT6_LVDS_CMOS_OUTPUT_POLARITY |
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