forked from M-Labs/artiq
drtio: fixes, basic TTL working in simulation
This commit is contained in:
parent
94e68dbae4
commit
ad042de954
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@ -45,7 +45,7 @@ class DRTIOSatellite(Module):
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class DRTIOMaster(Module):
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class DRTIOMaster(Module):
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def __init__(self, transceiver):
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def __init__(self, transceiver, channel_count=1024, fine_ts_width=3):
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self.submodules.link_layer = link_layer.LinkLayer(
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders)
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transceiver.encoder, transceiver.decoders)
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self.comb += [
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self.comb += [
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@ -53,7 +53,8 @@ class DRTIOMaster(Module):
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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]
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]
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self.submodules.rt_packets = rt_packets.RTPacketMaster(self.link_layer)
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self.submodules.rt_packets = rt_packets.RTPacketMaster(self.link_layer)
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self.submodules.rt_controller = rt_controller.RTController(self.rt_packets)
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self.submodules.rt_controller = rt_controller.RTController(
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self.rt_packets, channel_count, fine_ts_width)
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def get_csrs(self):
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def get_csrs(self):
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return self.rt_controller.get_csrs()
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return self.rt_controller.get_csrs()
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@ -25,16 +25,16 @@ class _KernelCSRs(AutoCSR):
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self.tsc_correction = CSRStorage(64)
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self.tsc_correction = CSRStorage(64)
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self.set_time = CSR()
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self.set_time = CSR()
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self.underflow_margin = CSRStorage(16, reset=50)
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self.underflow_margin = CSRStorage(16, reset=200)
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self.get_fifo_space = CSR()
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self.o_get_fifo_space = CSR()
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self.dbg_fifo_space = CSRStatus(16)
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self.o_dbg_fifo_space = CSRStatus(16)
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self.dbg_last_timestamp = CSRStatus(64)
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self.o_dbg_last_timestamp = CSRStatus(64)
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self.reset_channel_status = CSR()
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self.o_reset_channel_status = CSR()
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class RTController(Module):
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class RTController(Module):
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def __init__(self, rt_packets, channel_count=1024):
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def __init__(self, rt_packets, channel_count, fine_ts_width):
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self.kcsrs = _KernelCSRs()
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self.kcsrs = _KernelCSRs()
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self.submodules.counter = RTIOCounter(64)
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self.submodules.counter = RTIOCounter(64)
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@ -93,8 +93,8 @@ class RTController(Module):
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# TODO: collision, replace, busy
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# TODO: collision, replace, busy
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cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
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cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
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cond_underflow = (self.kcsrs.o_timestamp.storage - self.kcsrs.underflow_margin.storage
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cond_underflow = ((self.kcsrs.o_timestamp.storage - self.kcsrs.underflow_margin.storage
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< self.counter.value_sys)
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>> fine_ts_width) < self.counter.value_sys)
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cond_fifo_emptied = ((last_timestamps.dat_r
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cond_fifo_emptied = ((last_timestamps.dat_r
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< self.counter.value_sys - self.kcsrs.underflow_margin.storage)
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< self.counter.value_sys - self.kcsrs.underflow_margin.storage)
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& (last_timestamps.dat_r != 0))
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& (last_timestamps.dat_r != 0))
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@ -109,7 +109,7 @@ class RTController(Module):
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NextState("WRITE")
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NextState("WRITE")
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)
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)
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),
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),
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If(self.kcsrs.get_fifo_space.re,
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If(self.kcsrs.o_get_fifo_space.re,
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NextState("GET_FIFO_SPACE")
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NextState("GET_FIFO_SPACE")
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)
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)
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)
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)
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@ -154,9 +154,9 @@ class RTController(Module):
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)
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)
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self.comb += [
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self.comb += [
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self.kcsrs.dbg_fifo_space.status.eq(fifo_spaces.dat_r),
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self.kcsrs.o_dbg_fifo_space.status.eq(fifo_spaces.dat_r),
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self.kcsrs.dbg_last_timestamp.status.eq(last_timestamps.dat_r),
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self.kcsrs.o_dbg_last_timestamp.status.eq(last_timestamps.dat_r),
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If(self.kcsrs.reset_channel_status.re,
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If(self.kcsrs.o_reset_channel_status.re,
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fifo_spaces.dat_w.eq(0),
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fifo_spaces.dat_w.eq(0),
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fifo_spaces.we.eq(1),
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fifo_spaces.we.eq(1),
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last_timestamps.dat_w.eq(0),
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last_timestamps.dat_w.eq(0),
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@ -495,7 +495,10 @@ class RTPacketMaster(Module):
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tx_fsm.act("FIFO_SPACE",
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tx_fsm.act("FIFO_SPACE",
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tx_dp.send("fifo_space_request", channel=write_channel),
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tx_dp.send("fifo_space_request", channel=write_channel),
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tx_dp.stb.eq(1),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE_WRITE"))
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If(tx_dp.done,
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wfifo.re.eq(1),
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NextState("IDLE_WRITE")
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)
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)
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)
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tx_fsm.act("ECHO",
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tx_fsm.act("ECHO",
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tx_dp.send("echo_request"),
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tx_dp.send("echo_request"),
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@ -37,7 +37,7 @@ class DummyRXSynchronizer:
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class DUT(Module):
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class DUT(Module):
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def __init__(self, nwords):
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def __init__(self, nwords):
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self.ttl = Signal()
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self.ttl = Signal()
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self.transceivers = DummyTransceiverPair(2)
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self.transceivers = DummyTransceiverPair(nwords)
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self.submodules.master = DRTIOMaster(self.transceivers.alice)
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self.submodules.master = DRTIOMaster(self.transceivers.alice)
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@ -52,10 +52,36 @@ class TestFullStack(unittest.TestCase):
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dut = DUT(2)
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dut = DUT(2)
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kcsrs = dut.master.rt_controller.kcsrs
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kcsrs = dut.master.rt_controller.kcsrs
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def get_fifo_level():
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def get_fifo_space():
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for i in range(8):
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yield from kcsrs.o_get_fifo_space.write(1)
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yield from kcsrs.counter_update.write(1)
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yield
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print((yield from kcsrs.counter.read()))
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while (yield from kcsrs.o_status.read()) & 1:
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yield
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return (yield from kcsrs.o_dbg_fifo_space.read())
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run_simulation(dut, get_fifo_level(),
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def test():
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{"sys": 8, "rtio": 5, "rtio_rx": 5})
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print((yield from get_fifo_space()))
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yield from kcsrs.o_timestamp.write(550)
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yield from kcsrs.o_data.write(1)
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yield from kcsrs.o_we.write(1)
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yield
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status = 1
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while status:
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status = yield from kcsrs.o_status.read()
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print("status after write:", status)
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yield
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yield from kcsrs.o_timestamp.write(600)
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yield from kcsrs.o_data.write(0)
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yield from kcsrs.o_we.write(1)
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yield
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status = 1
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while status:
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status = yield from kcsrs.o_status.read()
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print("status after write:", status)
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yield
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for i in range(40):
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yield
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#print((yield from get_fifo_space()))
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run_simulation(dut, test(),
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{"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5}, vcd_name="foo.vcd")
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