forked from M-Labs/artiq
simplify tsc with no rtio/sys clk distinction
This commit is contained in:
parent
af0b94bb34
commit
ad000609ce
|
@ -15,7 +15,7 @@ class GrayCodeTransfer(Module):
|
||||||
|
|
||||||
# convert to Gray code
|
# convert to Gray code
|
||||||
value_gray_rtio = Signal(width, reset_less=True)
|
value_gray_rtio = Signal(width, reset_less=True)
|
||||||
self.sync += value_gray_rtio.eq(self.i ^ self.i[1:])
|
self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
|
||||||
# transfer to system clock domain
|
# transfer to system clock domain
|
||||||
value_gray_sys = Signal(width)
|
value_gray_sys = Signal(width)
|
||||||
value_gray_rtio.attr.add("no_retiming")
|
value_gray_rtio.attr.add("no_retiming")
|
||||||
|
|
|
@ -66,7 +66,7 @@ class Core(Module, AutoCSR):
|
||||||
interface=self.cri)
|
interface=self.cri)
|
||||||
self.submodules += outputs
|
self.submodules += outputs
|
||||||
self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts)
|
self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts)
|
||||||
self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts_sys + 16)
|
self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 16)
|
||||||
|
|
||||||
inputs = InputCollector(tsc, channels, "sync",
|
inputs = InputCollector(tsc, channels, "sync",
|
||||||
quash_channels=quash_channels,
|
quash_channels=quash_channels,
|
||||||
|
|
|
@ -1,8 +1,5 @@
|
||||||
from migen import *
|
from migen import *
|
||||||
|
|
||||||
from artiq.gateware.rtio.cdc import GrayCodeTransfer
|
|
||||||
|
|
||||||
|
|
||||||
class TSC(Module):
|
class TSC(Module):
|
||||||
def __init__(self, mode, glbl_fine_ts_width=0):
|
def __init__(self, mode, glbl_fine_ts_width=0):
|
||||||
self.glbl_fine_ts_width = glbl_fine_ts_width
|
self.glbl_fine_ts_width = glbl_fine_ts_width
|
||||||
|
@ -11,22 +8,10 @@ class TSC(Module):
|
||||||
self.coarse_ts = Signal(64 - glbl_fine_ts_width)
|
self.coarse_ts = Signal(64 - glbl_fine_ts_width)
|
||||||
self.full_ts = Signal(64)
|
self.full_ts = Signal(64)
|
||||||
|
|
||||||
# in sys domain
|
|
||||||
# monotonic, may lag behind the counter in the IO clock domain, but
|
|
||||||
# not be ahead of it.
|
|
||||||
self.coarse_ts_sys = Signal.like(self.coarse_ts)
|
|
||||||
self.full_ts_sys = Signal(64)
|
|
||||||
|
|
||||||
# in rtio domain
|
|
||||||
self.load = Signal()
|
self.load = Signal()
|
||||||
self.load_value = Signal.like(self.coarse_ts)
|
self.load_value = Signal.like(self.coarse_ts)
|
||||||
|
|
||||||
if mode == "async":
|
|
||||||
self.full_ts_cri = self.full_ts_sys
|
|
||||||
elif mode == "sync":
|
|
||||||
self.full_ts_cri = self.full_ts
|
self.full_ts_cri = self.full_ts
|
||||||
else:
|
|
||||||
raise ValueError
|
|
||||||
|
|
||||||
# # #
|
# # #
|
||||||
|
|
||||||
|
@ -35,14 +20,7 @@ class TSC(Module):
|
||||||
).Else(
|
).Else(
|
||||||
self.coarse_ts.eq(self.coarse_ts + 1)
|
self.coarse_ts.eq(self.coarse_ts + 1)
|
||||||
)
|
)
|
||||||
coarse_ts_cdc = GrayCodeTransfer(len(self.coarse_ts)) # from rtio to sys
|
|
||||||
self.submodules += coarse_ts_cdc
|
|
||||||
self.comb += [
|
|
||||||
coarse_ts_cdc.i.eq(self.coarse_ts),
|
|
||||||
self.coarse_ts_sys.eq(coarse_ts_cdc.o)
|
|
||||||
]
|
|
||||||
|
|
||||||
self.comb += [
|
self.comb += [
|
||||||
self.full_ts.eq(self.coarse_ts << glbl_fine_ts_width),
|
self.full_ts.eq(self.coarse_ts << glbl_fine_ts_width),
|
||||||
self.full_ts_sys.eq(self.coarse_ts_sys << glbl_fine_ts_width)
|
|
||||||
]
|
]
|
||||||
|
|
Loading…
Reference in New Issue