forked from M-Labs/artiq
rtio/sed/LaneDistributor: style
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@ -13,7 +13,8 @@ __all__ = ["LaneDistributor"]
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# 3. check status
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class LaneDistributor(Module):
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def __init__(self, lane_count, seqn_width, layout_payload, fine_ts_width, enable_spread=True, interface=None):
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def __init__(self, lane_count, seqn_width, layout_payload, fine_ts_width,
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enable_spread=True, interface=None):
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if lane_count & (lane_count - 1):
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raise NotImplementedError("lane count must be a power of 2")
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@ -21,8 +22,8 @@ class LaneDistributor(Module):
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interface = cri.Interface()
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self.cri = interface
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self.minimum_coarse_timestamp = Signal(64-fine_ts_width)
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self.lane_io = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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self.output = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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# # #
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@ -40,7 +41,7 @@ class LaneDistributor(Module):
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seqn = Signal(seqn_width)
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# distribute data to lanes
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for lio in self.lane_io:
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for lio in self.output:
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self.comb += [
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lio.seqn.eq(seqn),
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lio.payload.channel.eq(self.cri.chan_sel[:16]),
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@ -49,7 +50,7 @@ class LaneDistributor(Module):
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if hasattr(lio.payload, "address"):
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self.comb += lio.payload.address.eq(self.cri.address)
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if hasattr(lio.payload, "data"):
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self.comb += lio.payload.data.eq(self.cri.data)
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self.comb += lio.payload.data.eq(self.cri.o_data)
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# when timestamp arrives in cycle #1, prepare computations
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coarse_timestamp = Signal(64-fine_ts_width)
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@ -85,7 +86,7 @@ class LaneDistributor(Module):
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do_write.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & timestamp_above_lane_min),
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do_underflow.eq((self.cri.cmd == cri.commands["write"]) & ~timestamp_above_min),
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do_sequence_error.eq((self.cri.cmd == cri.commands["write"]) & timestamp_above_min & ~timestamp_above_lane_min),
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Array(lio.we for lio in self.lane_io)[use_lanen].eq(do_write)
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Array(lio.we for lio in self.output)[use_lanen].eq(do_write)
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]
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self.sync += [
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If(do_write,
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@ -99,7 +100,7 @@ class LaneDistributor(Module):
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# cycle #3, read status
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current_lane_writable = Signal()
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self.comb += [
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current_lane_writable.eq(Array(lio.writable for lio in self.lane_io)[current_lane]),
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current_lane_writable.eq(Array(lio.writable for lio in self.output)[current_lane]),
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o_status_wait.eq(~current_lane_writable)
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]
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self.sync += [
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@ -58,7 +58,7 @@ def simulate(input_events, wait=True):
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yield
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generators = [gen()]
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for n, lio in enumerate(dut.lane_io):
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for n, lio in enumerate(dut.output):
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lio.writable.reset = 1
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wait_time = 0
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if wait:
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