From ab9ca0ee0a6b77c051a5afd93de2ee6507dea2bf Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 2 Jan 2019 23:03:57 +0800 Subject: [PATCH] kasli: use 150MHz for DRTIO by default (Sayma compatibility) --- artiq/gateware/targets/kasli.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 3b61a1a3b..b5886e862 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -810,7 +810,7 @@ class _MasterBase(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, rtio_clk_freq=125e6, **kwargs): + def __init__(self, rtio_clk_freq=150e6, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -959,7 +959,7 @@ class _SatelliteBase(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, rtio_clk_freq=125e6, **kwargs): + def __init__(self, rtio_clk_freq=150e6, **kwargs): BaseSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon",