forked from M-Labs/artiq
add offset to coefficients as data
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@ -44,10 +44,8 @@ PHASER_ADDR_DAC1_TEST = 0x2c
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PHASER_ADDR_SERVO_CFG0 = 0x30
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PHASER_ADDR_SERVO_CFG0 = 0x30
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PHASER_ADDR_SERVO_CFG1 = 0x31
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PHASER_ADDR_SERVO_CFG1 = 0x31
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# 0x32 - 0x61 ab regs
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# 0x32 - 0x71 servo coefficients + offset data
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PHASER_ADDR_SERVO_COEFFICIENTS_BASE = 0x32
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PHASER_ADDR_SERVO_DATA_BASE = 0x32
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# 0x62 - 0x71 offset regs
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PHASER_ADDR_SERVO_OFFSET_BASE = 0x62
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PHASER_SEL_DAC = 1 << 0
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PHASER_SEL_DAC = 1 << 0
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@ -1133,13 +1131,10 @@ class PhaserChannel:
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if (profile < 0) or (profile > 3):
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if (profile < 0) or (profile > 3):
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raise ValueError("invalid profile index")
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raise ValueError("invalid profile index")
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# 24 byte-sized ab registers per channel and 6 (2 bytes * 3 coefficients) registers per profile
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# 24 byte-sized ab registers per channel and 6 (2 bytes * 3 coefficients) registers per profile
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addr = PHASER_ADDR_SERVO_COEFFICIENTS_BASE + (6 * profile) + (self.index * 24)
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addr = PHASER_ADDR_SERVO_DATA_BASE + (8 * profile) + (self.index * 32)
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for coef in [b0, b1, a1]:
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for data in [b0, b1, a1, offset]:
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self.phaser.write16(addr, coef)
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self.phaser.write16(addr, data)
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addr += 2
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addr += 2
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# 8 offset registers per channel and 2 registers per offset
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addr = PHASER_ADDR_SERVO_OFFSET_BASE + (2 * profile) + (self.index * 8)
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self.phaser.write16(addr, offset)
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@kernel
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@kernel
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def set_iir(self, profile, kp, ki=0., g=0., x_offset=0., y_offset=0.):
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def set_iir(self, profile, kp, ki=0., g=0., x_offset=0., y_offset=0.):
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