forked from M-Labs/artiq
rtio: allow specifying glbl_fine_ts_width externally
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5cf0693758
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@ -14,7 +14,8 @@ from artiq.gateware.rtio.input_collector import *
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class Core(Module, AutoCSR):
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def __init__(self, channels, lane_count=8, fifo_depth=128):
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def __init__(self, channels, lane_count=8, fifo_depth=128,
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glbl_fine_ts_width=None):
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self.cri = cri.Interface()
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self.reset = CSR()
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self.reset_phy = CSR()
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@ -53,10 +54,14 @@ class Core(Module, AutoCSR):
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self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy)
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# TSC
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glbl_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
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chan_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
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for channel in channels),
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max(rtlink.get_fine_ts_width(channel.interface.i)
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for channel in channels))
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if glbl_fine_ts_width is None:
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glbl_fine_ts_width = chan_fine_ts_width
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assert glbl_fine_ts_width >= chan_fine_ts_width
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coarse_ts = Signal(64-glbl_fine_ts_width)
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self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
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coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts))
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@ -94,7 +94,7 @@ class Master(MiniSoC, AMPSoC):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
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self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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