forked from M-Labs/artiq
rtio: fix CRI CSRs
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9acc7d135e
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@ -116,9 +116,3 @@ class KernelInitiator(Module, AutoCSR):
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self.o_data.we.eq(self.o_timestamp.re),
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]
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self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter))
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def get_csrs(self):
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return []
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def get_kernel_csrs(self):
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return AutoCSR.get_csrs(self)
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