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kasli: add SYSU variant and device_db

This commit is contained in:
Sebastien Bourdeauducq 2018-03-02 14:44:31 +08:00
parent 1c57d27ae2
commit a9daaad77b
4 changed files with 251 additions and 1 deletions

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@ -0,0 +1,125 @@
core_addr = "kasli-1.lab.m-labs.hk"
device_db = {
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1e-9}
},
"core_log": {
"type": "controller",
"host": "::1",
"port": 1068,
"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
},
"core_cache": {
"type": "local",
"module": "artiq.coredevice.cache",
"class": "CoreCache"
},
"core_dma": {
"type": "local",
"module": "artiq.coredevice.dma",
"class": "CoreDMA"
},
"i2c_switch0": {
"type": "local",
"module": "artiq.coredevice.i2c",
"class": "PCA9548",
"arguments": {"address": 0xe0}
},
"i2c_switch1": {
"type": "local",
"module": "artiq.coredevice.i2c",
"class": "PCA9548",
"arguments": {"address": 0xe2}
},
}
for i in range(40):
device_db["ttl" + str(i)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": i},
}
device_db.update(
spi_urukul0={
"type": "local",
"module": "artiq.coredevice.spi2",
"class": "SPIMaster",
"arguments": {"channel": 40}
},
ttl_urukul0_io_update={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 41}
},
ttl_urukul0_sw0={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 42}
},
ttl_urukul0_sw1={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 43}
},
ttl_urukul0_sw2={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 44}
},
ttl_urukul0_sw3={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 45}
},
urukul0_cpld={
"type": "local",
"module": "artiq.coredevice.urukul",
"class": "CPLD",
"arguments": {
"spi_device": "spi_urukul0",
"io_update_device": "ttl_urukul0_io_update",
"refclk": 125e6,
"clk_sel": 0
}
}
)
for i in range(4):
device_db["urukul0_ch" + str(i)] = {
"type": "local",
"module": "artiq.coredevice.ad9910",
"class": "AD9910",
"arguments": {
"pll_n": 32,
"chip_select": 4 + i,
"cpld_device": "urukul0_cpld",
"sw_device": "ttl_urukul0_sw" + str(i)
}
}
device_db.update(
led0={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 46}
},
led1={
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 47}
}
)

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@ -0,0 +1,21 @@
from artiq.experiment import *
class IdleKernel(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("led0")
@kernel
def run(self):
start_time = now_mu() + self.core.seconds_to_mu(500*ms)
while self.core.get_rtio_counter_mu() < start_time:
pass
self.core.reset()
while True:
self.led0.pulse(250*ms)
delay(125*ms)
self.led0.pulse(125*ms)
delay(125*ms)
self.led0.pulse(125*ms)
delay(250*ms)

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@ -0,0 +1,49 @@
from artiq.experiment import *
class UrukulTest(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("urukul0_cpld")
self.setattr_device("urukul0_ch0")
self.setattr_device("urukul0_ch1")
self.setattr_device("urukul0_ch2")
self.setattr_device("urukul0_ch3")
self.setattr_device("led0")
@kernel
def run(self):
self.core.reset()
self.led0.on()
delay(5*ms)
self.led0.off()
self.urukul0_cpld.init()
self.urukul0_ch0.init()
self.urukul0_ch1.init()
self.urukul0_ch2.init()
self.urukul0_ch3.init()
delay(1000*us)
self.urukul0_ch0.set(100*MHz)
self.urukul0_ch0.sw.on()
self.urukul0_ch0.set_att(10.)
delay(1000*us)
self.urukul0_ch1.set(10*MHz, 0.5)
self.urukul0_ch1.sw.on()
self.urukul0_ch1.set_att(0.)
delay(1000*us)
self.urukul0_ch2.set(400*MHz)
self.urukul0_ch2.sw.on()
self.urukul0_ch2.set_att(0.)
delay(1000*us)
self.urukul0_ch3.set(1*MHz)
self.urukul0_ch3.sw.on()
self.urukul0_ch3.set_att(20.)
while True:
self.urukul0_ch0.sw.pulse(5*ms)
delay(5*ms)

View File

@ -304,6 +304,59 @@ class Opticlock(_StandaloneBase):
self.add_rtio(rtio_channels)
class SYSU(_StandaloneBase):
def __init__(self, **kwargs):
_StandaloneBase.__init__(self, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
platform = self.platform
platform.add_extension(_urukul("eem1", "eem0"))
platform.add_extension(_dio("eem2"))
platform.add_extension(_dio("eem3"))
platform.add_extension(_dio("eem4"))
platform.add_extension(_dio("eem5"))
platform.add_extension(_dio("eem6"))
# EEM clock fan-out from Si5324, not MMCX
self.comb += platform.request("clk_sel").eq(1)
rtio_channels = []
for i in range(40):
eem_offset, port = divmod(i, 8)
pads = platform.request("eem{}".format(2 + eem_offset), port)
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi2.SPIMaster(self.platform.request("eem1_spi_p"),
self.platform.request("eem1_spi_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
pads = platform.request("eem1_dds_reset")
self.specials += DifferentialOutput(0, pads.p, pads.n)
for signal in "io_update sw0 sw1 sw2 sw3".split():
pads = platform.request("eem1_{}".format(signal))
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in (1, 2):
sfp_ctl = platform.request("sfp_ctl", i)
phy = ttl_simple.Output(sfp_ctl.led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels)
class Master(MiniSoC, AMPSoC):
mem_map = {
"cri_con": 0x10000000,
@ -542,13 +595,15 @@ def main():
soc_kasli_args(parser)
parser.set_defaults(output_dir="artiq_kasli")
parser.add_argument("-V", "--variant", default="opticlock",
help="variant: opticlock/master/satellite "
help="variant: opticlock/sysu/master/satellite "
"(default: %(default)s)")
args = parser.parse_args()
variant = args.variant.lower()
if variant == "opticlock":
cls = Opticlock
elif variant == "sysu":
cls = SYSU
elif variant == "master":
cls = Master
elif variant == "satellite":