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sayma_rtm: drive ref_lo_clk_sel, and set clk muxes early

This commit is contained in:
Robert Jördens 2018-06-12 20:00:12 +02:00
parent aff7fa008f
commit a9a25f2605
3 changed files with 7 additions and 3 deletions
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4
artiq/firmware/libboard_artiq/hmc830_7043.rs
View File

@ -4,13 +4,15 @@ mod clock_mux {
const CLK_SRC_EXT_SEL : u8 = 1 << 0; const CLK_SRC_EXT_SEL : u8 = 1 << 0;
const REF_CLK_SRC_SEL : u8 = 1 << 1; const REF_CLK_SRC_SEL : u8 = 1 << 1;
const DAC_CLK_SRC_SEL : u8 = 1 << 2; const DAC_CLK_SRC_SEL : u8 = 1 << 2;
const REF_LO_CLK_SEL : u8 = 1 << 3;
pub fn init() { pub fn init() {
unsafe { unsafe {
csr::clock_mux::out_write( csr::clock_mux::out_write(
1*CLK_SRC_EXT_SEL | // use ext clk from sma 1*CLK_SRC_EXT_SEL | // use ext clk from sma
1*REF_CLK_SRC_SEL | 1*REF_CLK_SRC_SEL |
1*DAC_CLK_SRC_SEL); 1*DAC_CLK_SRC_SEL |
0*REF_LO_CLK_SEL);
} }
} }
} }

4
artiq/gateware/targets/sayma_rtm.py
View File

@ -124,7 +124,9 @@ class SaymaRTM(Module):
self.submodules.clock_mux = gpio.GPIOOut(Cat( self.submodules.clock_mux = gpio.GPIOOut(Cat(
platform.request("clk_src_ext_sel"), platform.request("clk_src_ext_sel"),
platform.request("ref_clk_src_sel"), platform.request("ref_clk_src_sel"),
platform.request("dac_clk_src_sel"))) platform.request("dac_clk_src_sel"),
platform.request("ref_lo_clk_sel")),
reset_out=0b0111)
csr_devices.append("clock_mux") csr_devices.append("clock_mux")
# UART loopback # UART loopback

2
conda/artiq-dev/meta.yaml
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@ -14,7 +14,7 @@ requirements:
run: run:
- python >=3.5.3,<3.6 - python >=3.5.3,<3.6
- setuptools 33.1.1 - setuptools 33.1.1
- migen 0.7 py35_44+gitca28f4e - migen 0.7 py35_46+git5947224c
- misoc 0.11 py35_20+git2436a68d - misoc 0.11 py35_20+git2436a68d
- jesd204b 0.7 - jesd204b 0.7
- microscope - microscope