forked from M-Labs/artiq
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
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94c20dfd4d
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a93decdef2
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@ -333,6 +333,8 @@ class Master(MiniSoC, AMPSoC):
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += self.disable_si5324_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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DRTIOMaster(self.drtio_transceiver.channels[0]))
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@ -379,16 +381,20 @@ class Master(MiniSoC, AMPSoC):
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# Never running out of stupid features, GTs on A7 make you pack
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# unrelated transceiver PLLs into one GTPE2_COMMON yourself.
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def create_qpll(self):
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# The GTP acts up if you send any glitch to its
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# clock input, even while the PLL is held in reset.
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self.disable_si5324_ibuf = Signal(reset=1)
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self.disable_si5324_ibuf.attr.add("keep")
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si5324_clkout = self.platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_CEB=self.disable_si5324_ibuf,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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# Note precisely the rules Xilinx made up:
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# refclksel=0b001 GTREFCLK0 selected
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# refclksel=0b010 GTREFCLK1 selected
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# but if only one clock used, then it must be 001.
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# but if only one clock is used, then it must be 001.
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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@ -433,10 +439,12 @@ class Satellite(BaseSoC):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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disable_si5324_ibuf = Signal(reset=1)
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disable_si5324_ibuf.attr.add("keep")
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si5324_clkout = platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_CEB=disable_si5324_ibuf,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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qpll_drtio_settings = QPLLSettings(
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@ -454,6 +462,9 @@ class Satellite(BaseSoC):
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += disable_si5324_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.drtio_transceiver.channels[0], rtio_channels))
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