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kasli_sawgmaster: correctly tune DDS and SAWG

This commit is contained in:
Sebastien Bourdeauducq 2019-01-24 19:37:14 +08:00
parent f8b39b0b9a
commit a92cc91dcb
2 changed files with 11 additions and 3 deletions
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3
artiq/examples/kasli_sawgmaster/device_db.py
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@ -89,7 +89,8 @@ for i in range(4):
"module": "artiq.coredevice.ad9910", "module": "artiq.coredevice.ad9910",
"class": "AD9910", "class": "AD9910",
"arguments": { "arguments": {
"pll_n": 26, # 975MHz sample rate "pll_n": 16, # 600MHz sample rate
"pll_vco": 2,
"chip_select": 4 + i, "chip_select": 4 + i,
"cpld_device": "urukul0_cpld", "cpld_device": "urukul0_cpld",
"sw_device": "ttl_urukul0_sw" + str(i) "sw_device": "ttl_urukul0_sw" + str(i)

11
artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py
View File

@ -17,6 +17,13 @@ class SinesUrukulSayma(EnvExperiment):
@kernel @kernel
def run(self): def run(self):
f = 9*MHz
dds_ftw = self.urukul_chs[0].frequency_to_ftw(f)
sawg_ftw = self.sawgs[0].frequency0.to_mu(f)
if dds_ftw != sawg_ftw:
print("DDS and SAWG FTWs do not match:", dds_ftw, sawg_ftw)
return
# Note: when testing sync, do not reboot Urukul, as it is not # Note: when testing sync, do not reboot Urukul, as it is not
# synchronized to the FPGA (yet). # synchronized to the FPGA (yet).
self.core.reset() self.core.reset()
@ -24,7 +31,7 @@ class SinesUrukulSayma(EnvExperiment):
for urukul_ch in self.urukul_chs: for urukul_ch in self.urukul_chs:
delay(1*ms) delay(1*ms)
urukul_ch.init() urukul_ch.init()
urukul_ch.set(9*MHz, amplitude=0.5) urukul_ch.set_mu(dds_ftw, asf=urukul_ch.amplitude_to_asf(0.5))
urukul_ch.set_att(6.) urukul_ch.set_att(6.)
urukul_ch.sw.on() urukul_ch.sw.on()
@ -43,7 +50,7 @@ class SinesUrukulSayma(EnvExperiment):
for sawg in self.sawgs: for sawg in self.sawgs:
delay(1*ms) delay(1*ms)
sawg.amplitude1.set(.4) sawg.amplitude1.set(.4)
sawg.frequency0.set(9*MHz) sawg.frequency0.set_mu(sawg_ftw)
while self.drtio_is_up(): while self.drtio_is_up():
pass pass